Cypress manual Pin Configurations Ball BGA Pinout, CY7C1354C 256K ×, CY7C1356C 512K x

Page 4

CY7C1354C

CY7C1356C

Pin Configurations (continued)

119-Ball BGA Pinout

CY7C1354C (256K × 36)

1

2

3

4

5

6

7

A

VDDQ

A

A

NC/18M

A

A

VDDQ

B

NC/576M

CE2

A

ADV/LD

A

CE3

NC

C

NC/1G

A

A

VDD

A

A

NC

D

DQc

DQPc

VSS

NC

VSS

DQPb

DQb

E

DQc

DQc

VSS

CE

1

VSS

DQb

DQb

F

VDDQ

DQc

VSS

VSS

DQb

VDDQ

OE

G

DQc

DQc

c

A

b

DQb

DQb

BW

BW

H

DQc

DQc

VSS

VSS

DQb

DQb

WE

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQd

DQd

VSS

CLK

VSS

DQa

DQa

L

DQd

DQd

d

NC

a

DQa

DQa

BW

BW

M

VDDQ

DQd

VSS

VSS

DQa

VDDQ

CEN

N

DQd

DQd

VSS

A1

VSS

DQa

DQa

P

DQd

DQPd

VSS

A0

VSS

DQPa

DQa

R

NC/144M

A

MODE

VDD

NC

A

NC/288M

T

NC

NC/72M

A

A

A

NC/36M

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

CY7C1356C (512K x 18)

1

2

3

4

5

6

7

A

VDDQ

A

A

NC/18M

A

A

VDDQ

B

NC/576M

CE2

A

A

3

NC

ADV/LD

CE

C

NC/1G

A

A

VDD

A

A

NC

D

DQb

NC

VSS

NC

VSS

DQPa

NC

E

NC

DQb

VSS

1

VSS

NC

DQa

CE

F

VDDQ

NC

VSS

VSS

DQa

VDDQ

OE

G

NC

DQb

b

A

VSS

NC

DQa

BW

H

DQb

NC

VSS

VSS

DQa

NC

WE

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQb

VSS

CLK

VSS

NC

DQa

L

DQb

NC

VSS

NC

DQa

NC

BW

a

M

VDDQ

DQb

VSS

VSS

NC

VDDQ

CEN

N

DQb

NC

VSS

A1

VSS

DQa

NC

P

NC

DQPb

VSS

A0

VSS

NC

DQa

R

NC/144M

A

MODE

VDD

NC

A

NC/288M

T

NC/72M

A

A

NC/36M

A

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document #: 38-05538 Rev. *G

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Contents Features Logic Block Diagram-CY7C1354C 256K xFunctional Description1 Cypress Semiconductor CorporationLogic Block Diagram-CY7C1356C 512K x Maximum Access Time Maximum Operating CurrentSelection Guide 250 MHz 200 MHz 166 MHz UnitPin Configurations Pin Tqfp Pinout 512K ×CY7C1354C 256K × Pin Configurations Ball BGA PinoutCY7C1356C 512K x Pin Configurations Ball Fbga Pinout CY7C1356C 512K ×Pin Definitions Single Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Sleep Mode Partial Write Cycle Description2, 3, 4Function CY7C1354C Function CY7C1356CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size Instruction Code DescriptionBoundary Scan Exit Order 256K × Bit # Ball IDBoundary Scan Exit Order 512K × B10J10 K10Electrical Characteristics Over the Operating Range14 Maximum RatingsOperating Range Ambient RangeCapacitance16 Thermal ResistanceAC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range 18 250 200 166 Parameter Description Unit Min MaxADV/LD BWX DataOut DQ A6 A7Switching Waveforms NOP,STALL and Deselect Cycles23, 24ZZ Mode Timing27 DON’T CareOrdering Information CY7C1354C CY7C1356C Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd ECN No Issue Date Orig. Description of Change Document History