Cypress CY7C1354C, CY7C1356C Scan Register Sizes, Identification Codes, Register Name Bit Size

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				CY7C1354C
				CY7C1356C
				CY7C1356C


Scan Register Sizes

Register Name			Bit Size (x36)	Bit Size (x18)

Instruction			3	3

Bypass			1	1

ID			32	32

Boundary Scan Order (119-ball BGA package)			69	69

Boundary Scan Order (165-ball FBGA package)			69	69

Identification Codes

Instruction	Code	Description
EXTEST	000	Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
		TDO. Forces all SRAM outputs to High-Z state.
IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
		operation does not affect SRAM operation.
SAMPLE Z	010	Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
		Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
		Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.

Document #: 38-05538 Rev. *G

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Contents Functional Description1 FeaturesLogic Block Diagram-CY7C1354C 256K x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1356C 512K xMaximum Access Time Maximum Operating Current 250 MHz 200 MHz 166 MHz UnitPin Configurations Pin Tqfp Pinout 512K ×CY7C1356C 512K x Pin Configurations Ball BGA PinoutCY7C1354C 256K × Pin Configurations Ball Fbga Pinout CY7C1356C 512K ×Pin Definitions Single Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Function CY7C1354C Sleep ModePartial Write Cycle Description2, 3, 4 Function CY7C1356CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block DiagramTAP Controller State Diagram Bypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBoundary Scan Exit Order 256K × Bit # Ball IDJ10 Boundary Scan Exit Order 512K ×B10 K10Operating Range Electrical Characteristics Over the Operating Range14Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance16Thermal Resistance 3V I/O Test LoadSwitching Characteristics Over the Operating Range 18 250 200 166 Parameter Description Unit Min MaxOut DQ ADV/LD BWXData A6 A7Switching Waveforms NOP,STALL and Deselect Cycles23, 24ZZ Mode Timing27 DON’T CareOrdering Information CY7C1354C CY7C1356C Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd ECN No Issue Date Orig. Description of Change Document History