Cypress CY7C1356C, CY7C1354C manual Boundary Scan Exit Order 256K ×, Bit # Ball ID

Page 15

CY7C1354C

CY7C1356C

Boundary Scan Exit Order (256K × 36)

Bit #

119-ball ID

165-ball ID

1

K4

B6

 

 

 

2

H4

B7

 

 

 

3

M4

A7

 

 

 

4

F4

B8

 

 

 

5

B4

A8

 

 

 

6

G4

A9

 

 

 

7

C3

B10

 

 

 

8

B3

A10

 

 

 

9

D6

C11

 

 

 

10

H7

E10

 

 

 

11

G6

F10

 

 

 

12

E6

G10

 

 

 

13

D7

D10

 

 

 

14

E7

D11

 

 

 

15

F6

E11

 

 

 

16

G7

F11

 

 

 

17

H6

G11

 

 

 

18

T7

H11

 

 

 

19

K7

J10

 

 

 

20

L6

K10

 

 

 

21

N6

L10

 

 

 

22

P7

M10

 

 

 

23

N7

J11

 

 

 

24

M6

K11

 

 

 

25

L7

L11

 

 

 

26

K6

M11

 

 

 

27

P6

N11

 

 

 

28

T4

R11

 

 

 

29

A3

R10

 

 

 

30

C5

P10

 

 

 

31

B5

R9

 

 

 

32

A5

P9

 

 

 

33

C6

R8

 

 

 

34

A6

P8

 

 

 

35

P4

R6

 

 

 

36

N4

P6

 

 

 

37

R6

R4

 

 

 

38

T5

P4

 

 

 

39

T3

R3

 

 

 

40

R2

P3

 

 

 

41

R3

R1

 

 

 

42

P2

N1

 

 

 

43

P1

L2

 

 

 

Boundary Scan Exit Order (256K × 36) (continued)

Bit #

119-ball ID

165-ball ID

44

L2

K2

 

 

 

45

K1

J2

 

 

 

46

N2

M2

 

 

 

47

N1

M1

 

 

 

48

M2

L1

 

 

 

49

L1

K1

 

 

 

50

K2

J1

 

 

 

51

Not Bonded

Not Bonded

 

(Preset to 1)

(Preset to 1)

52

H1

G2

 

 

 

53

G2

F2

 

 

 

54

E2

E2

 

 

 

55

D1

D2

 

 

 

56

H2

G1

 

 

 

57

G1

F1

 

 

 

58

F2

E1

 

 

 

59

E1

D1

 

 

 

60

D2

C1

 

 

 

61

C2

B2

 

 

 

62

A2

A2

 

 

 

63

E4

A3

 

 

 

64

B2

B3

 

 

 

65

L3

B4

 

 

 

66

G3

A4

 

 

 

67

G5

A5

 

 

 

68

L5

B5

 

 

 

69

B6

A6

 

 

 

Document #: 38-05538 Rev. *G

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1354C 256K x Functional Description1250 MHz 200 MHz 166 MHz Unit Logic Block Diagram-CY7C1356C 512K xMaximum Access Time Maximum Operating Current Selection Guide512K × Pin Configurations Pin Tqfp PinoutPin Configurations Ball BGA Pinout CY7C1354C 256K ×CY7C1356C 512K x CY7C1356C 512K × Pin Configurations Ball Fbga PinoutPin Definitions Functional Overview Single Read AccessesBurst Read Accesses Single Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1356C Sleep ModePartial Write Cycle Description2, 3, 4 Function CY7C1354CTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Description Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeBit # Ball ID Boundary Scan Exit Order 256K ×K10 Boundary Scan Exit Order 512K ×B10 J10Ambient Range Electrical Characteristics Over the Operating Range14Maximum Ratings Operating Range3V I/O Test Load Capacitance16Thermal Resistance AC Test Loads and Waveforms250 200 166 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 18A6 A7 ADV/LD BWXData Out DQNOP,STALL and Deselect Cycles23, 24 Switching WaveformsDON’T Care ZZ Mode Timing27Ordering Information CY7C1354C CY7C1356C Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball BGA 14 x 22 x 2.4 mmSoldernotespad Type NON-SOLDER Mask Defined Nsmd Document History ECN No Issue Date Orig. Description of Change