Cypress CY7C1354C, CY7C1356C manual Boundary Scan Exit Order 512K ×, B10, J10, K10, P10

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CY7C1354C

CY7C1356C

Boundary Scan Exit Order (512K × 18)

Bit #	119-ball ID	165-ball ID
1	K4	B6

2	H4	B7

3	M4	A7

4	F4	B8

5	B4	A8

6	G4	A9

7	C3	B10

8	B3	A10

9	T2	A11

10	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
11	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
12	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
13	D6	C11

14	E7	D11

15	F6	E11

16	G7	F11

17	H6	G11

18	T7	H11

19	K7	J10

20	L6	K10

21	N6	L10

22	P7	M10

23	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
24	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
25	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
26	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
27	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
28	T6	R11

29	A3	R10

30	C5	P10

31	B5	R9

32	A5	P9

33	C6	R8

34	A6	P8

35	P4	R6

36	N4	P6

37	R6	R4

38	T5	P4

Boundary Scan Exit Order (512K × 18) (continued)

Bit #	119-ball ID	165-ball ID
39	T3	R3

40	R2	P3

41	R3	R1

42	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
43	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
44	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
45	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
46	P2	N1

47	N1	M1

48	M2	L1

49	L1	K1

50	K2	J1

51	Not Bonded	Not Bonded
	(Preset to 1)	(Preset to 1)
52	H1	G2

53	G2	F2

54	E2	E2

55	D1	D2

56	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
57	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
58	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
59	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
60	Not Bonded	Not Bonded
	(Preset to 0)	(Preset to 0)
61	C2	B2

62	A2	A2

63	E4	A3

64	B2	B3

65	Not Bonded	Not Bonded
	(Preset to 0	(Preset to 0)
66	G3	Not Bonded
		(Preset to 0)
67	Not Bonded	A4
	(Preset to 0
68	L5	B5

69	B6	A6

Document #: 38-05538 Rev. *G

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Contents Features Logic Block Diagram-CY7C1354C 256K xFunctional Description1 Cypress Semiconductor CorporationLogic Block Diagram-CY7C1356C 512K x Maximum Access Time Maximum Operating CurrentSelection Guide 250 MHz 200 MHz 166 MHz UnitPin Configurations Pin Tqfp Pinout 512K ×CY7C1354C 256K × Pin Configurations Ball BGA PinoutCY7C1356C 512K x Pin Configurations Ball Fbga Pinout CY7C1356C 512K ×Pin Definitions Single Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Sleep Mode Partial Write Cycle Description2, 3, 4Function CY7C1354C Function CY7C1356CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size Instruction Code DescriptionBoundary Scan Exit Order 256K × Bit # Ball IDBoundary Scan Exit Order 512K × B10J10 K10Electrical Characteristics Over the Operating Range14 Maximum RatingsOperating Range Ambient RangeCapacitance16 Thermal ResistanceAC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range 18 250 200 166 Parameter Description Unit Min MaxADV/LD BWX DataOut DQ A6 A7Switching Waveforms NOP,STALL and Deselect Cycles23, 24ZZ Mode Timing27 DON’T CareOrdering Information CY7C1354C CY7C1356C Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd ECN No Issue Date Orig. Description of Change Document History