Cypress CY7C1354C, CY7C1356C manual Document History, ECN No Issue Date Orig. Description of Change

Page 28

CY7C1354C

CY7C1356C

Document History Page

Document Title: CY7C1354C/CY7C1356C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05538

REV.

ECN No.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

242032

See ECN

RKF

New data sheet

 

 

 

 

 

*A

278130

See ECN

RKF

Changed Boundary Scan order to match the B Rev of these devices

 

 

 

 

Changed TQFP pkg to Lead-free TQFP in Ordering Information section

 

 

 

 

Added comment of Lead-free BG and BZ packages availability

 

 

 

 

 

*B

284431

See ECN

VBL

Changed ISB1 and ISB3 from DC Characteristic table as follows

 

 

 

 

ISB1: 225 mA-> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA

 

 

 

 

ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA

 

 

 

 

Add BG and BZ pkg lead-free part numbers to ordering info section

*C

320834

See ECN

PCI

Changed 225 MHz to 250 MHz

 

 

 

 

Address expansion pins/balls in the pinouts for all packages are modified as

 

 

 

 

per JEDEC standard

 

 

 

 

Unshaded frequencies of 250, 200, 166 MHz in AC/DC Tables and Selection

 

 

 

 

Guide

 

 

 

 

Changed ΘJA and ΘJC for TQFP Package from 25 and 9 °C/W to 29.41 and

 

 

 

 

6.13 °C/W respectively

 

 

 

 

Changed ΘJA and ΘJC for BGA Package from 25 and 6 °C/W to 34.1 and

 

 

 

 

14.0 °C/W respectively

 

 

 

 

Changed ΘJA and ΘJC for FBGA Package from 27 and 6 °C/W to 16.8 and

 

 

 

 

3.0 °C/W respectively

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Added Lead-Free product information

 

 

 

 

Updated Ordering Information Table

 

 

 

 

Changed from Preliminary to Final

*D

351895

See ECN

PCI

Changed ISB2 from 35 to 40 mA

 

 

 

 

Updated Ordering Information Table

*E

377095

See ECN

PCI

Modified test condition in note# 15 from VDDQ < VDD to VDDQ ≤ VDD

*F

408298

See ECN

RXU

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Changed three-state to tri-state.

 

 

 

 

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in

 

 

 

 

the Electrical Characteristics Table.

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table.

*G

501793

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

 

 

 

 

AC Switching Characteristics table.

 

 

 

 

Updated the Ordering Information table.

Document #: 38-05538 Rev. *G

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Contents Features Logic Block Diagram-CY7C1354C 256K xFunctional Description1 Cypress Semiconductor CorporationLogic Block Diagram-CY7C1356C 512K x Maximum Access Time Maximum Operating CurrentSelection Guide 250 MHz 200 MHz 166 MHz UnitPin Configurations Pin Tqfp Pinout 512K ×CY7C1354C 256K × Pin Configurations Ball BGA PinoutCY7C1356C 512K x Pin Configurations Ball Fbga Pinout CY7C1356C 512K ×Pin Definitions Single Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Sleep Mode Partial Write Cycle Description2, 3, 4Function CY7C1354C Function CY7C1356CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size Instruction Code DescriptionBoundary Scan Exit Order 256K × Bit # Ball IDBoundary Scan Exit Order 512K × B10J10 K10Electrical Characteristics Over the Operating Range14 Maximum RatingsOperating Range Ambient RangeCapacitance16 Thermal ResistanceAC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range 18 250 200 166 Parameter Description Unit Min MaxADV/LD BWX DataOut DQ A6 A7Switching Waveforms NOP,STALL and Deselect Cycles23, 24ZZ Mode Timing27 DON’T CareOrdering Information CY7C1354C CY7C1356C Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd ECN No Issue Date Orig. Description of Change Document History
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