Cypress CY7C1380C, CY7C1382C manual Serial data-out to the Jtag circuit . Delivers data

Page 11

 

 

 

 

 

 

CY7C1380C

 

 

 

 

 

 

CY7C1382C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1382C:Pin Definitions (continued)

 

 

 

 

 

 

 

 

 

 

Name

TQFP

 

BGA

fBGA

I/O

Description

 

 

 

 

 

 

VDDQ

4,11,20,27,54,

A1,A7,F1,F7,

C3,C9,D3,D9,

I/O Power Sup-

Power supply for the I/O circuitry.

 

61,70,

J1,J7,M1,M7,

E3,E9,

ply

 

 

 

77

 

U1,U7

F3,F9,G3,

 

 

 

 

 

 

 

G9,J3,J9,

 

 

 

 

 

 

 

K3,K9,L3,

 

 

 

 

 

 

 

L9,M3,M9,N3,

 

 

 

 

 

 

 

N9

 

 

 

 

 

 

 

 

 

 

MODE

31

 

R3

R1

Input-

Selects Burst Order. When tied to GND selects

 

 

 

 

 

Static

linear burst sequence. When tied to VDD or left

 

 

 

 

 

 

floating selects interleaved burst sequence. This is

 

 

 

 

 

 

a strap pin and should remain static during device

 

 

 

 

 

 

operation. Mode Pin has an internal pull-up.

 

 

 

 

 

 

 

TDO

-

 

U5

P7

JTAG serial

Serial data-out to the JTAG circuit. Delivers data

 

 

 

 

 

output

on the negative edge of TCK. If the JTAG feature is

 

 

 

 

 

Synchronous

not being utilized, this pin should be left uncon-

 

 

 

 

 

 

nected. This pin is not available on TQFP

 

 

 

 

 

 

packages.

 

 

 

 

 

 

 

TDI

-

 

U3

P5

JTAG serial

Serial data-In to the JTAG circuit. Sampled on the

 

 

 

 

 

input

rising edge of TCK. If the JTAG feature is not being

 

 

 

 

 

Synchronous

utilized, this pin can be left floating or connected to

 

 

 

 

 

 

VDD through a pull up resistor. This pin is not avail-

 

 

 

 

 

 

able on TQFP packages.

 

 

 

 

 

 

 

TMS

-

 

U2

R5

JTAG serial

Serial data-In to the JTAG circuit. Sampled on the

 

 

 

 

 

input

rising edge of TCK. If the JTAG feature is not being

 

 

 

 

 

Synchronous

utilized, this pin can be disconnected or connected

 

 

 

 

 

 

to VDD. This pin is not available on TQFP packages.

TCK

-

 

U4

R7

JTAG-Clock

Clock input to the JTAG circuitry. If the JTAG

 

 

 

 

 

 

feature is not being utilized, this pin must be

 

 

 

 

 

 

connected to VSS. This pin is not available on TQFP

 

 

 

 

 

 

packages.

 

 

 

 

 

 

 

NC

1,2,3,6,7,

 

B1,B7,

A5,B1,B4,

-

No Connects. Not internally connected to the die.

 

14,16,25,

 

C1,C7,

C1,C2,C10,D1

 

 

 

 

28,29,30,

 

D2,D4,

,D10,

 

 

 

 

38,39,

 

D7,E1,

E1,E10,F1,

 

 

 

 

51,52,53,

 

E6,H2,

F10,G1,

 

 

 

 

56,57,66,

 

F2,G1,

G10,H1,H3,H9

 

 

 

 

75,78,79,

 

G6,H7,

,H10,J2,J11,

 

 

 

 

95,96

 

J3,J5,K1,

K2,

 

 

 

 

 

K6,L4,L2,L7,

K11,L2,L1,M2,

 

 

 

 

 

 

M6,

M11,

 

 

 

 

 

N2,L7,P1,P6,

N2,N10,N5,N7

 

 

 

 

 

 

R1,

N11,P1,A1,

 

 

 

 

 

 

R5,R7,

B11,

 

 

 

 

 

 

T1,T4,U6

P2,R2

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-05237 Rev. *D

Page 11 of 36

[+] Feedback

Page 10 Page 12
Image 11
Page 10 Page 12
Contents 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1382C 1M x Logic Block Diagram CY7C1380C 512K xCY7C1382C 1M x Pin ConfigurationsCY7C1380C 512K X CY7C1382C 512K x NC / 72M NC / 36MNC / 72M NC / 288MTqfp BGA CY7C1380C-Pin DefinitionsAddress Strobe from Controller, sampled on Power supply inputs to the core of the deAddress Strobe from Processor, sampled On the rising edge of CLK, active LOW. WhenSerial data-out to the Jtag circuit . Delivers Power supply for the I/O circuitrySelects Burst Order . When tied to GND Ground for the I/O circuitryCY7C1382CPin Definitions Address Strobe from Processor, sampled on Rising edge of CLK, active LOW . When assertedZZ sleep Input, active High . When asserted Power supply inputs to the core of the deviceSerial data-out to the Jtag circuit . Delivers data Functional Overview Single Read AccessesCE2 Adsp Adsc ADV Write CLK Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics AddressBWE Truth Table for Read/Write5CLK Adsp Adsc ADV Write Function CY7C1380CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Bypass RegisterBoundary Scan Register Identification ID RegisterTAP Timing TAP AC Switching Characteristics Over the operating Range9Parameter Description Test Conditions MIN MAX Units 3V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Codes Identification Register DefinitionsScan Register Sizes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x J10 Ball fBGA Boundary Scan Order CY7C1380C 512K xA10 F10 G10Ball fBGA Boundary Scan Order CY7C1382C 1M x Ambient Range Electrical Characteristics Over the Operating Range12Maximum Ratings Operating RangeFBGA Unit Thermal Resistance14Capacitance Parameter Description Test Conditions5V I/O Test Load AC Test Loads and Waveforms3V I/O Test Load Min Max Unit Switching Characteristics Over the Operating Range19Read Cycle Timing21 Switching WaveformsWrite Cycle Timing21 CLZ Read/Write Cycle Timing21, 23ZZ Mode Timing 25 CY7C1382C-167AI CY7C1380C-167BGI Ordering InformationCY7C1382C-250AC CY7C1380C-250BGC Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package DiagramsLead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams REV ECN no Issue Date Orig. Description of ChangeDocument History
Top Page Image Contents