Cypress CY7C1382C manual CY7C1380C-Pin Definitions, Tqfp BGA

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CY7C1380C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1382C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1380C–Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

TQFP

 

BGA

fBGA

I/O

Description

 

 

 

 

 

 

 

 

 

A0, A1 , A

37,36,32,

 

P4,N4,

R6,P6,A2,

Input-

Address Inputs used to select one of the

 

 

 

 

 

 

 

 

 

 

33,34,35,

 

A2,B2,

A10,B2,

Synchronous

256K address locations. Sampled at the rising

 

 

 

 

 

 

 

 

 

 

42,43,44,45,

 

C2,R2,

B10,N6,P3,P4,

 

edge of the CLK if ADSP or ADSC is active

 

 

 

 

 

 

 

 

 

 

46,47,48,

 

A3,B3,C3,

P8,P9,P10,

 

LOW, and CE1, CE2, and CE3 [2]are sampled

 

 

 

 

 

 

 

 

 

 

49,50,81,

 

T3,T4,A5,B5,

P11,R3,R4,R8,

 

active. A1: A0 are fed to the two-bit counter..

 

 

 

 

 

 

 

 

 

 

82,99,100

 

C5,

R9,R10,R11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T5,A6,B6,C6,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A,

 

B

93,94,95,

 

L5,G5,

B5,A5,A4,

Input-

Byte Write Select Inputs, active LOW.

 

BW

BW

 

 

 

 

 

 

 

 

 

 

96

 

G3,L3

B4

Synchronous

Qualified with BWE to conduct byte writes to the

 

BWC,BWD

 

 

 

 

 

 

SRAM. Sampled on the rising edge of CLK.

 

 

 

 

 

 

 

88

 

H4

B7

Input-

Global Write Enable Input, active LOW.

 

GW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

When asserted LOW on the rising edge of CLK,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a global write is conducted (ALL bytes are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

written, regardless of the values on BWX and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BWE).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

87

 

M4

A7

Input-

Byte Write Enable Input, active LOW. Sam-

 

BWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

pled on the rising edge of CLK. This signal must

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

be asserted LOW to conduct a byte write.

 

 

 

 

 

 

 

 

 

CLK

89

 

K4

B6

Input-

Clock Input. Used to capture all synchronous

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

inputs to the device. Also used to increment the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

burst counter when ADV is asserted LOW,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

during a burst operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

98

 

E4

A3

Input-

Chip Enable 1 Input, active LOW. Sampled on

 

CE1

 

 

 

 

 

Synchronous

the rising edge of CLK. Used in conjunction with

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2 and CE3 to select/deselect the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADSP is ignored if CE1 is HIGH.

 

CE2[2]

97

 

-

B3

Input-

Chip Enable 2 Input, active HIGH. Sampled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

on the rising edge of CLK. Used in conjunction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

with CE1 and CE3 to select/deselect the device.

 

 

3[2]

92

 

-

A6

Input-

Chip Enable 3 Input, active LOW. Sampled on

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

the rising edge of CLK. Used in conjunction with

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE1 and CE2 to select/deselect the device.Not

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

available for AJ package version.Not

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

connected for BGA. Where referenced,

CE

3 is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

assumed active throughout this document for

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BGA.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

86

 

F4

B8

Input-

Output Enable, asynchronous input, active

 

OE

 

 

 

 

 

Asynchronous

LOW. Controls the direction of the I/O pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When LOW, the I/O pins behave as outputs.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When deasserted HIGH, I/O pins are tri-stated,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and act as input data pins. OE is masked during

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the first clock of a read cycle when emerging

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

from a deselected state.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

83

 

G4

A9

Input-

Advance Input signal, sampled on the rising

 

ADV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

edge of CLK, active LOW. When asserted, it

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

automatically increments the address in a burst

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-05237 Rev. *D

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Contents Selection Guide FeaturesFunctional Description1 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz UnitLogic Block Diagram CY7C1380C 512K x Logic Block Diagram CY7C1382C 1M xPin Configurations CY7C1380C 512K XCY7C1382C 1M x NC / 72M NC / 36M CY7C1382C 512K xNC / 288M NC / 72MCY7C1380C-Pin Definitions Tqfp BGAOn the rising edge of CLK, active LOW. When Power supply inputs to the core of the deAddress Strobe from Processor, sampled Address Strobe from Controller, sampled onGround for the I/O circuitry Power supply for the I/O circuitrySelects Burst Order . When tied to GND Serial data-out to the Jtag circuit . DeliversCY7C1382CPin Definitions Power supply inputs to the core of the device Rising edge of CLK, active LOW . When assertedZZ sleep Input, active High . When asserted Address Strobe from Processor, sampled onSerial data-out to the Jtag circuit . Delivers data Single Read Accesses Functional OverviewAddress Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics CE2 Adsp Adsc ADV Write CLKFunction CY7C1380C Truth Table for Read/Write5CLK Adsp Adsc ADV Write BWETAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagIdentification ID Register Bypass RegisterBoundary Scan Register TAP Instruction SetTAP AC Switching Characteristics Over the operating Range9 TAP Timing3V TAP AC Test Conditions 5V TAP AC Output Load EquivalentParameter Description Test Conditions MIN MAX Units Identification Register Definitions Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x F10 G10 Ball fBGA Boundary Scan Order CY7C1380C 512K xA10 J10Ball fBGA Boundary Scan Order CY7C1382C 1M x Operating Range Electrical Characteristics Over the Operating Range12Maximum Ratings Ambient RangeParameter Description Test Conditions Thermal Resistance14Capacitance FBGA UnitAC Test Loads and Waveforms 3V I/O Test Load5V I/O Test Load Switching Characteristics Over the Operating Range19 Min Max UnitSwitching Waveforms Read Cycle Timing21Write Cycle Timing21 Read/Write Cycle Timing21, 23 CLZZZ Mode Timing 25 Ordering Information CY7C1382C-250AC CY7C1380C-250BGCCY7C1382C-167AI CY7C1380C-167BGI Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams Issue Date Orig. Description of Change Document HistoryREV ECN no
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