Cypress CY7C1380C manual Package Diagrams, Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101

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CY7C1380C

CY7C1382C

Package Diagrams

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

16.00±0.20

DIMENSIONS ARE IN MILLIMETERS.

14.00±0.10

100

1

22.00±0.20

20.00±0.10

30

31

81

80

0.30±0.08

0.65

TYP.

51

50

12° ±1° (8X)

1.40±0.05

SEE DETAIL

A

0.20 MAX.

R 0.08 MIN. 0.20 MAX.

0.25

GAUGE PLANE

0° -7°

0.60±0.15

0° MIN.

R 0.08 MIN. 0.20 MAX.

0.20 MIN.

STAND-OFF

0.05MIN.

0.15MAX.

SEATING PLANE

1.60 MAX.

0.10

1.00 REF.

DETAIL A

51-85050-*A

Document #: 38-05237 Rev. *D

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© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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Contents Functional Description1 FeaturesSelection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz UnitLogic Block Diagram CY7C1382C 1M x Logic Block Diagram CY7C1380C 512K xPin Configurations CY7C1380C 512K XCY7C1382C 1M x CY7C1382C 512K x NC / 72M NC / 36MNC / 72M NC / 288MTqfp BGA CY7C1380C-Pin DefinitionsAddress Strobe from Processor, sampled Power supply inputs to the core of the deOn the rising edge of CLK, active LOW. When Address Strobe from Controller, sampled onSelects Burst Order . When tied to GND Power supply for the I/O circuitryGround for the I/O circuitry Serial data-out to the Jtag circuit . DeliversCY7C1382CPin Definitions ZZ sleep Input, active High . When asserted Rising edge of CLK, active LOW . When assertedPower supply inputs to the core of the device Address Strobe from Processor, sampled onSerial data-out to the Jtag circuit . Delivers data Functional Overview Single Read AccessesZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDAddress CE2 Adsp Adsc ADV Write CLKCLK Adsp Adsc ADV Write Truth Table for Read/Write5Function CY7C1380C BWEIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramBoundary Scan Register Bypass RegisterIdentification ID Register TAP Instruction SetTAP Timing TAP AC Switching Characteristics Over the operating Range93V TAP AC Test Conditions 5V TAP AC Output Load EquivalentParameter Description Test Conditions MIN MAX Units Identification Register Definitions Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x A10 Ball fBGA Boundary Scan Order CY7C1380C 512K xF10 G10 J10Ball fBGA Boundary Scan Order CY7C1382C 1M x Maximum Ratings Electrical Characteristics Over the Operating Range12Operating Range Ambient RangeCapacitance Thermal Resistance14Parameter Description Test Conditions FBGA UnitAC Test Loads and Waveforms 3V I/O Test Load5V I/O Test Load Min Max Unit Switching Characteristics Over the Operating Range19Read Cycle Timing21 Switching WaveformsWrite Cycle Timing21 CLZ Read/Write Cycle Timing21, 23ZZ Mode Timing 25 Ordering Information CY7C1382C-250AC CY7C1380C-250BGCCY7C1382C-167AI CY7C1380C-167BGI Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package DiagramsLead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams Issue Date Orig. Description of Change Document HistoryREV ECN no