Cypress CY7C1382C, CY7C1380C manual AC Test Loads and Waveforms, 3V I/O Test Load, 5V I/O Test Load

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CY7C1380C

CY7C1382C

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT

3.3V

R = 317Ω

ALL INPUT PULSES

VDD

Z0

= 50Ω

OUTPUT

RL

= 50Ω

10%

90%

5 pF

R = 351Ω

GND

≤ 1ns

VL = 1.5V

INCLUDING

(c)

(a)

JIG AND

(b)

SCOPE

2.5V I/O Test Load

OUTPUT

2.5V

R = 1667Ω

ALL INPUT PULSES

VDD

Z0

= 50Ω

OUTPUT

RL

= 50Ω

10%

90%

5 pF

R =1538Ω

GND

≤ 1ns

VL = 1.25V

90%

10%

≤ 1ns

90%

10%

≤ 1ns

	INCLUDING								(c)


(a)	JIG AND				(b)
	SCOPE				(b)
	SCOPE

Document #: 38-05237 Rev. *D

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Contents Selection Guide FeaturesFunctional Description1 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz UnitLogic Block Diagram CY7C1380C 512K x Logic Block Diagram CY7C1382C 1M xCY7C1382C 1M x Pin ConfigurationsCY7C1380C 512K X NC / 72M NC / 36M CY7C1382C 512K xNC / 288M NC / 72MCY7C1380C-Pin Definitions Tqfp BGAOn the rising edge of CLK, active LOW. When Power supply inputs to the core of the deAddress Strobe from Processor, sampled Address Strobe from Controller, sampled onGround for the I/O circuitry Power supply for the I/O circuitrySelects Burst Order . When tied to GND Serial data-out to the Jtag circuit . DeliversCY7C1382CPin Definitions Power supply inputs to the core of the device Rising edge of CLK, active LOW . When assertedZZ sleep Input, active High . When asserted Address Strobe from Processor, sampled onSerial data-out to the Jtag circuit . Delivers data Single Read Accesses Functional OverviewAddress Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics CE2 Adsp Adsc ADV Write CLKFunction CY7C1380C Truth Table for Read/Write5CLK Adsp Adsc ADV Write BWETAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagIdentification ID Register Bypass RegisterBoundary Scan Register TAP Instruction SetTAP AC Switching Characteristics Over the operating Range9 TAP TimingParameter Description Test Conditions MIN MAX Units 3V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Codes Identification Register DefinitionsScan Register Sizes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x F10 G10 Ball fBGA Boundary Scan Order CY7C1380C 512K xA10 J10Ball fBGA Boundary Scan Order CY7C1382C 1M x Operating Range Electrical Characteristics Over the Operating Range12Maximum Ratings Ambient RangeParameter Description Test Conditions Thermal Resistance14Capacitance FBGA Unit5V I/O Test Load AC Test Loads and Waveforms3V I/O Test Load Switching Characteristics Over the Operating Range19 Min Max UnitSwitching Waveforms Read Cycle Timing21Write Cycle Timing21 Read/Write Cycle Timing21, 23 CLZZZ Mode Timing 25 CY7C1382C-167AI CY7C1380C-167BGI Ordering InformationCY7C1382C-250AC CY7C1380C-250BGC Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams REV ECN no Issue Date Orig. Description of ChangeDocument History