Cypress CY7C1380C Identification Register Definitions, Scan Register Sizes, Identification Codes

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							CY7C1380C
							CY7C1382C


	Identification Register Definitions

	INSTRUCTION FIELD		CY7C1380C		CY7C1382C	DESCRIPTION
	INSTRUCTION FIELD		(512KX36)		(1MX18)

	Revision Number (31:29)		010		0100	Describes the version number.

	Device Depth (28:24)		01010		1010	Reserved for Internal Use

	Device Width (23:18)		000000		000000	Defines memory type and architecture

	Cypress Device ID (17:12)		100101		010101	Defines width and density

	Cypress JEDEC ID Code (11:1)		00000110100		00000110100	Allows unique identification of SRAM vendor.

	ID Register Presence Indicator (0)		1		1	Indicates the presence of an ID register.

Scan Register Sizes

	REGISTER NAME				BIT SIZE(X36)		BIT SIZE(X18)
	Instruction				3		3
	Bypass				1		1
	ID				32		32
	Boundary Scan Order				72		72

Identification Codes

INSTRUCTION	CODE	DESCRIPTION

EXTEST	000	Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
		Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and
		TDO. This operation does not affect SRAM operations.

SAMPLE Z	010	Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
		Forces all SRAM output drivers to a High-Z state.

RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
		Does not affect SRAM operation. This instruction does not implement 1149.1 preload
		function and is therefore not 1149.1 compliant.

RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect
		SRAM operations.

Document #: 38-05237 Rev. *D

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Contents 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1382C 1M x Logic Block Diagram CY7C1380C 512K xCY7C1380C 512K X Pin ConfigurationsCY7C1382C 1M x CY7C1382C 512K x NC / 72M NC / 36MNC / 72M NC / 288MTqfp BGA CY7C1380C-Pin DefinitionsAddress Strobe from Controller, sampled on Power supply inputs to the core of the deAddress Strobe from Processor, sampled On the rising edge of CLK, active LOW. WhenSerial data-out to the Jtag circuit . Delivers Power supply for the I/O circuitrySelects Burst Order . When tied to GND Ground for the I/O circuitryCY7C1382CPin Definitions Address Strobe from Processor, sampled on Rising edge of CLK, active LOW . When assertedZZ sleep Input, active High . When asserted Power supply inputs to the core of the deviceSerial data-out to the Jtag circuit . Delivers data Functional Overview Single Read AccessesCE2 Adsp Adsc ADV Write CLK Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics AddressBWE Truth Table for Read/Write5CLK Adsp Adsc ADV Write Function CY7C1380CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Bypass RegisterBoundary Scan Register Identification ID RegisterTAP Timing TAP AC Switching Characteristics Over the operating Range95V TAP AC Output Load Equivalent 3V TAP AC Test ConditionsParameter Description Test Conditions MIN MAX Units Scan Register Sizes Identification Register DefinitionsIdentification Codes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x J10 Ball fBGA Boundary Scan Order CY7C1380C 512K xA10 F10 G10Ball fBGA Boundary Scan Order CY7C1382C 1M x Ambient Range Electrical Characteristics Over the Operating Range12Maximum Ratings Operating RangeFBGA Unit Thermal Resistance14Capacitance Parameter Description Test Conditions3V I/O Test Load AC Test Loads and Waveforms5V I/O Test Load Min Max Unit Switching Characteristics Over the Operating Range19Read Cycle Timing21 Switching WaveformsWrite Cycle Timing21 CLZ Read/Write Cycle Timing21, 23ZZ Mode Timing 25 CY7C1382C-250AC CY7C1380C-250BGC Ordering InformationCY7C1382C-167AI CY7C1380C-167BGI Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package DiagramsLead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams Document History Issue Date Orig. Description of ChangeREV ECN no