Cypress CY7C1382C, CY7C1380C manual Maximum Ratings, Operating Range, Ambient Range

Page 24

CY7C1380C

CY7C1382C

Maximum Ratings

(Above which the useful life may be impaired. For user guide- lines, not tested.)

Storage Temperature

–65°C to +150°C

Ambient Temperature with

 

 

Power Applied

–55°C to +125°C

Supply Voltage on VDD Relative to GND

........ –0.3V to +4.6V

DC Voltage Applied to Outputs

 

 

in Tri-State

–0.5V to VDDQ + 0.5V

DC Input Voltage

–0.5V to VDD + 0.5V

Current into Outputs (LOW)

20 mA

Static Discharge Voltage

>2001V

(per MIL-STD-883, Method 3015)

 

Latch-up Current

>200 mA

Operating Range

 

Ambient

 

 

Range

Temperature

VDD

VDDQ

Commercial

0°C to +70°C

3.3V – 5%/+10%

2.5V – 5%

 

 

 

to VDD

Industrial

-40°C to +85°C

 

Electrical Characteristics Over the Operating Range[12, 13]

Parameter

Description

Test Conditions

Min.

Max.

Unit

VDD

Power Supply Voltage

 

 

3.135

3.6

V

VDDQ

I/O Supply Voltage

VDDQ = 3.3V

 

3.135

VDD

V

 

 

VDDQ = 2.5V

 

2.375

2.625

V

VOH

Output HIGH Voltage

VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA

2.4

 

V

 

 

VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA

2.0

 

V

VOL

Output LOW Voltage

VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA

 

0.4

V

 

 

VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA

 

0.4

V

VIH

Input HIGH Voltage[12]

VDDQ = 3.3V

 

2.0

VDD + 0.3V

V

 

 

VDDQ = 2.5V

 

1.7

VDD + 0.3V

V

VIL

Input LOW Voltage[12]

VDDQ = 3.3V

 

–0.3

0.8

V

 

 

VDDQ = 2.5V

 

–0.3

0.7

V

IX

Input Load Current ex-

GND VI VDDQ

 

–5

5

A

 

cept ZZ and MODE

 

 

 

 

 

 

Input Current of MODE

Input = VSS

 

–30

 

A

 

 

Input = VDD

 

 

5

A

 

Input Current of ZZ

Input = VSS

 

–30

 

A

 

 

Input = VDD

 

 

5

A

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

 

–5

5

A

IDD

VDD Operating Supply

VDD = Max., IOUT = 0 mA,

4.0-ns cycle, 250 MHz

 

350

mA

 

Current

f = fMAX = 1/tCYC

4.4-ns cycle, 225 MHz

 

325

mA

 

 

 

5.0-ns cycle, 200 MHz

 

300

mA

 

 

 

 

 

 

 

 

 

 

6.0-ns cycle, 167 MHz

 

275

mA

 

 

 

 

 

 

 

 

 

 

7.5-ns cycle, 133 MHz

 

245

mA

 

 

 

 

 

 

 

ISB1

Automatic CE

VDD = Max, Device Deselected,

4.0-ns cycle, 250 MHz

 

120

mA

 

Power-down

VIN VIH or VIN VIL

4.4-ns cycle, 225 MHz

 

110

mA

 

Current—TTL Inputs

f = fMAX = 1/tCYC

 

 

 

 

 

5.0-ns cycle, 200 MHz

 

100

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6.0-ns cycle, 167 MHz

 

90

mA

 

 

 

 

 

 

 

 

 

 

7.5-ns cycle, 133 MHz

 

85

mA

 

 

 

 

 

 

 

ISB2

Automatic CE

VDD = Max, Device Deselected,

All speeds

 

70

mA

 

Power-down

VIN 0.3V or VIN > VDDQ – 0.3V,

 

 

 

 

 

Current—CMOS Inputs

f = 0

 

 

 

 

Document #: 38-05237 Rev. *D

Page 24 of 36

[+] Feedback

Image 24
Contents Features Functional Description1Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz UnitLogic Block Diagram CY7C1380C 512K x Logic Block Diagram CY7C1382C 1M xPin Configurations CY7C1380C 512K XCY7C1382C 1M x NC / 72M NC / 36M CY7C1382C 512K xNC / 288M NC / 72MCY7C1380C-Pin Definitions Tqfp BGAPower supply inputs to the core of the de Address Strobe from Processor, sampledOn the rising edge of CLK, active LOW. When Address Strobe from Controller, sampled onPower supply for the I/O circuitry Selects Burst Order . When tied to GNDGround for the I/O circuitry Serial data-out to the Jtag circuit . DeliversCY7C1382CPin Definitions Rising edge of CLK, active LOW . When asserted ZZ sleep Input, active High . When assertedPower supply inputs to the core of the device Address Strobe from Processor, sampled onSerial data-out to the Jtag circuit . Delivers data Single Read Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD ZZ Mode Electrical CharacteristicsAddress CE2 Adsp Adsc ADV Write CLKTruth Table for Read/Write5 CLK Adsp Adsc ADV WriteFunction CY7C1380C BWETAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagBypass Register Boundary Scan RegisterIdentification ID Register TAP Instruction SetTAP AC Switching Characteristics Over the operating Range9 TAP Timing3V TAP AC Test Conditions 5V TAP AC Output Load EquivalentParameter Description Test Conditions MIN MAX Units Identification Register Definitions Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x Ball fBGA Boundary Scan Order CY7C1380C 512K x A10F10 G10 J10Ball fBGA Boundary Scan Order CY7C1382C 1M x Electrical Characteristics Over the Operating Range12 Maximum RatingsOperating Range Ambient RangeThermal Resistance14 CapacitanceParameter Description Test Conditions FBGA UnitAC Test Loads and Waveforms 3V I/O Test Load5V I/O Test Load Switching Characteristics Over the Operating Range19 Min Max UnitSwitching Waveforms Read Cycle Timing21Write Cycle Timing21 Read/Write Cycle Timing21, 23 CLZZZ Mode Timing 25 Ordering Information CY7C1382C-250AC CY7C1380C-250BGCCY7C1382C-167AI CY7C1380C-167BGI Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams Issue Date Orig. Description of Change Document HistoryREV ECN no