Cypress CY7C1382C, CY7C1380C manual 3V TAP AC Test Conditions, 5V TAP AC Output Load Equivalent

Page 18

CY7C1380C

CY7C1382C

3.3V TAP AC Test Conditions

2.5V TAP AC Test Conditions

Input pulse levels	VSS to 3.3V
Input rise and fall times	1ns
Input timing reference levels	1.5V
Output reference levels	1.5V
Test load termination supply voltage	1.5V

Input pulse levels	VSS to 2.5V
Input rise and fall time	1ns
Input timing reference levels	1.25V
Output reference levels	1.25V
Test load termination supply voltage	........1.25V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Output Load Equivalent

1.5V

1.25V

50Ω

50Ω

TDO

TDO

ZO= 50Ω

20pF

ZO= 50Ω

20pF

TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; Vdd = 3.3V ±0.165V unless otherwise noted)[11]

PARAMETER	DESCRIPTION	TEST CONDITIONS		MIN	MAX	UNITS

VOH1	Output HIGH Voltage	IOH = -4.0 mA,VDDQ = 3.3V		2.4		V
		IOH = -1.0 mA,VDDQ = 2.5V		2.0		V
VOH2	Output HIGH Voltage	IOH = -100 µA	VDDQ = 3.3V	2.9		V
			VDDQ = 2.5V	2.1		V
VOL1	Output LOW Voltage	IOL = 8.0 mA	VDDQ = 3.3V		0.4	V
			VDDQ = 2.5V		0.4	V
VOL2	Output LOW Voltage	IOL = 100 µA	VDDQ = 3.3V		0.2	V
			VDDQ = 2.5V		0.2	V
VIH	Input HIGH Voltage		VDDQ = 3.3V	2.0	VDD + 0.3	V
			VDDQ = 2.5V	1.7	VDD + 0.3	V
VIL	Input LOW Voltage		VDDQ = 3.3V	-0.3	0.8	V
			VDDQ = 2.5V	-0.3	0.7	V
IX	Input Load Current	GND < VIN < VDDQ		-5	5	µA

Note:

11. All voltages referenced to VSS (GND).

Document #: 38-05237 Rev. *D

Page 18 of 36

[+] Feedback

Image 18

Contents Selection Guide FeaturesFunctional Description1 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz UnitLogic Block Diagram CY7C1380C 512K x Logic Block Diagram CY7C1382C 1M xPin Configurations CY7C1380C 512K XCY7C1382C 1M x NC / 72M NC / 36M CY7C1382C 512K xNC / 288M NC / 72MCY7C1380C-Pin Definitions Tqfp BGAOn the rising edge of CLK, active LOW. When Power supply inputs to the core of the deAddress Strobe from Processor, sampled Address Strobe from Controller, sampled onGround for the I/O circuitry Power supply for the I/O circuitrySelects Burst Order . When tied to GND Serial data-out to the Jtag circuit . DeliversCY7C1382CPin Definitions Power supply inputs to the core of the device Rising edge of CLK, active LOW . When assertedZZ sleep Input, active High . When asserted Address Strobe from Processor, sampled onSerial data-out to the Jtag circuit . Delivers data Single Read Accesses Functional OverviewAddress Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics CE2 Adsp Adsc ADV Write CLKFunction CY7C1380C Truth Table for Read/Write5CLK Adsp Adsc ADV Write BWETAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagIdentification ID Register Bypass RegisterBoundary Scan Register TAP Instruction SetTAP AC Switching Characteristics Over the operating Range9 TAP Timing3V TAP AC Test Conditions 5V TAP AC Output Load EquivalentParameter Description Test Conditions MIN MAX Units Identification Register Definitions Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x F10 G10 Ball fBGA Boundary Scan Order CY7C1380C 512K xA10 J10Ball fBGA Boundary Scan Order CY7C1382C 1M x Operating Range Electrical Characteristics Over the Operating Range12Maximum Ratings Ambient RangeParameter Description Test Conditions Thermal Resistance14Capacitance FBGA UnitAC Test Loads and Waveforms 3V I/O Test Load5V I/O Test Load Switching Characteristics Over the Operating Range19 Min Max UnitSwitching Waveforms Read Cycle Timing21Write Cycle Timing21 Read/Write Cycle Timing21, 23 CLZZZ Mode Timing 25 Ordering Information CY7C1382C-250AC CY7C1380C-250BGCCY7C1382C-167AI CY7C1380C-167BGI Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams Issue Date Orig. Description of Change Document HistoryREV ECN no