Cypress manual Ordering Information, CY7C1382C-250AC CY7C1380C-250BGC

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CY7C1380C

CY7C1382C

Ordering Information

Speed	Ordering Code	Package	Part and Package Type	Operating
(MHz)	Ordering Code	Name	Part and Package Type	Range

250	CY7C1380C-250AC	A101	100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)	Commercial
	CY7C1382C-250AC
	CY7C1380C-250BGC	BG119	119 PBGA
	CY7C1382C-250BGC
	CY7C1380C-250BZC	BB165A	165 fBGA
	CY7C1382C-250BZC
225	CY7C1380C-225AC	A101	100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

	CY7C1382C-225AC
	CY7C1380C-225BGC	BG119	119 PBGA
	CY7C1382C-225BGC
	CY7C1380C-225BZC	BB165A	165 fBGA
	CY7C1382C-225BZC
200	CY7C1380C-200AC	A101	100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
	CY7C1382C-200AC
	CY7C1380C-200BGC	BG119	119 PBGA

	CY7C1382C-200BGC
	CY7C1380C-200BZC	BB165A	165 fBGA
	CY7C1382C-200BZC

167	CY7C1380C-167AC	A101	100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
	CY7C1382C-167AC
	CY7C1380C-167BGC	BG119	119 PBGA

	CY7C1382C-167BGC
	CY7C1380C-167BZC	BB165A	165 fBGA
	CY7C1382C-167BZC
133	CY7C1380C-133AC	A101	100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

167	CY7C1380C-167AI	A101	100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)	Industrial
	CY7C1382C-167AI
	CY7C1380C-167BGI	BG119	119 PBGA
	CY7C1382C-167BGI
	CY7C1380C-167BZI	BB165A	165 fBGA

	CY7C1382C-167BZI

Shaded areas contain advance information.

Please contact your local sales representative for availability of these parts.

Document #: 38-05237 Rev. *D

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Contents Features Functional Description1Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz UnitLogic Block Diagram CY7C1380C 512K x Logic Block Diagram CY7C1382C 1M xCY7C1382C 1M x Pin ConfigurationsCY7C1380C 512K X NC / 72M NC / 36M CY7C1382C 512K xNC / 288M NC / 72MCY7C1380C-Pin Definitions Tqfp BGAPower supply inputs to the core of the de Address Strobe from Processor, sampledOn the rising edge of CLK, active LOW. When Address Strobe from Controller, sampled onPower supply for the I/O circuitry Selects Burst Order . When tied to GNDGround for the I/O circuitry Serial data-out to the Jtag circuit . DeliversCY7C1382CPin Definitions Rising edge of CLK, active LOW . When asserted ZZ sleep Input, active High . When assertedPower supply inputs to the core of the device Address Strobe from Processor, sampled onSerial data-out to the Jtag circuit . Delivers data Single Read Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD ZZ Mode Electrical CharacteristicsAddress CE2 Adsp Adsc ADV Write CLKTruth Table for Read/Write5 CLK Adsp Adsc ADV WriteFunction CY7C1380C BWETAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagBypass Register Boundary Scan RegisterIdentification ID Register TAP Instruction SetTAP AC Switching Characteristics Over the operating Range9 TAP TimingParameter Description Test Conditions MIN MAX Units 3V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Codes Identification Register DefinitionsScan Register Sizes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x Ball fBGA Boundary Scan Order CY7C1380C 512K x A10F10 G10 J10Ball fBGA Boundary Scan Order CY7C1382C 1M x Electrical Characteristics Over the Operating Range12 Maximum RatingsOperating Range Ambient RangeThermal Resistance14 CapacitanceParameter Description Test Conditions FBGA Unit5V I/O Test Load AC Test Loads and Waveforms3V I/O Test Load Switching Characteristics Over the Operating Range19 Min Max UnitSwitching Waveforms Read Cycle Timing21Write Cycle Timing21 Read/Write Cycle Timing21, 23 CLZZZ Mode Timing 25 CY7C1382C-167AI CY7C1380C-167BGI Ordering InformationCY7C1382C-250AC CY7C1380C-250BGC Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams REV ECN no Issue Date Orig. Description of ChangeDocument History