Cypress CY7C1382C, CY7C1380C Document History, REV ECN no, Issue Date Orig. Description of Change

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CY7C1380C

CY7C1382C

Document History Page

Document Title: CY7C1380C/CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM

Document Number: 38-05237

REV.	ECN NO.	Issue Date	Orig. of	Description of Change
REV.	ECN NO.	Issue Date	Change	Description of Change

**	116277	08/27/02	SKX	New Data Sheet

*A	121540	11/21/02	DSG	Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122
				(BB165A) to rev. *C
*B	121797	11/21/02	CJM	Added 7C1380C-133 spec
				Updated Ordering Information
*C	128904	09/11/03	DPM	Changed ordering of notes
				Updated JTAG Boundary Scan order
				Removed Pipelined Read/Write Timing diagram
				Added tPOWER specification in Switching Characteristics table
*D	206081	02/13/04	RKF	Final Datasheet

Document #: 38-05237 Rev. *D

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Contents Features Functional Description1Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz UnitLogic Block Diagram CY7C1380C 512K x Logic Block Diagram CY7C1382C 1M xPin Configurations CY7C1380C 512K XCY7C1382C 1M x NC / 72M NC / 36M CY7C1382C 512K xNC / 288M NC / 72MCY7C1380C-Pin Definitions Tqfp BGAPower supply inputs to the core of the de Address Strobe from Processor, sampledOn the rising edge of CLK, active LOW. When Address Strobe from Controller, sampled onPower supply for the I/O circuitry Selects Burst Order . When tied to GNDGround for the I/O circuitry Serial data-out to the Jtag circuit . DeliversCY7C1382CPin Definitions Rising edge of CLK, active LOW . When asserted ZZ sleep Input, active High . When assertedPower supply inputs to the core of the device Address Strobe from Processor, sampled onSerial data-out to the Jtag circuit . Delivers data Single Read Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD ZZ Mode Electrical CharacteristicsAddress CE2 Adsp Adsc ADV Write CLKTruth Table for Read/Write5 CLK Adsp Adsc ADV WriteFunction CY7C1380C BWETAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagBypass Register Boundary Scan RegisterIdentification ID Register TAP Instruction SetTAP AC Switching Characteristics Over the operating Range9 TAP Timing3V TAP AC Test Conditions 5V TAP AC Output Load EquivalentParameter Description Test Conditions MIN MAX Units Identification Register Definitions Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x Ball fBGA Boundary Scan Order CY7C1380C 512K x A10F10 G10 J10Ball fBGA Boundary Scan Order CY7C1382C 1M x Electrical Characteristics Over the Operating Range12 Maximum RatingsOperating Range Ambient RangeThermal Resistance14 CapacitanceParameter Description Test Conditions FBGA UnitAC Test Loads and Waveforms 3V I/O Test Load5V I/O Test Load Switching Characteristics Over the Operating Range19 Min Max UnitSwitching Waveforms Read Cycle Timing21Write Cycle Timing21 Read/Write Cycle Timing21, 23 CLZZZ Mode Timing 25 Ordering Information CY7C1382C-250AC CY7C1380C-250BGCCY7C1382C-167AI CY7C1380C-167BGI Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams Issue Date Orig. Description of Change Document HistoryREV ECN no