Cypress CY7C1380C, CY7C1382C manual Interleaved Burst Address Table Mode = Floating or VDD

Page 13

CY7C1380C

CY7C1382C

Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported.

Interleaved Burst Address Table (MODE = Floating or VDD)

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

 

 

 

 

01

00

11

10

 

 

 

 

10

11

00

01

 

 

 

 

11

10

01

00

 

 

 

 

Linear Burst

Address

Table

 

(MODE = GND)

 

 

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

 

 

 

 

01

10

11

00

 

 

 

 

10

11

00

01

 

 

 

 

11

00

01

10

 

 

 

 

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW

.

ZZ Mode Electrical Characteristics

 

Parameter

 

Description

 

 

 

 

 

 

 

Test Conditions

 

 

 

Min.

 

 

Max.

 

Unit

 

IDDZZ

 

Snooze mode standby current

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

 

 

 

60mA

 

mA

 

tZZS

 

Device operation to ZZ

 

 

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

 

 

 

2tCYC

 

ns

 

tZZREC

 

ZZ recovery time

 

 

 

 

 

ZZ < 0.2V

 

 

 

 

 

 

2tCYC

 

 

 

 

 

 

ns

 

tZZI

 

ZZ Active to snooze current

 

 

 

 

 

This parameter is sampled

 

 

 

 

 

 

 

 

2tCYC

 

ns

 

tRZZI

 

ZZ Inactive to exit snooze current

 

 

 

This parameter is sampled

 

 

0

 

 

 

 

 

 

 

ns

 

Truth Table[ 3, 4, 5, 6, 7, 8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

Add. Used

 

CE

1

CE2

 

CE

3

ZZ

 

ADSP

 

 

ADSC

 

 

ADV

 

 

WRITE

 

 

 

OE

 

CLK

DQ

 

Deselect Cycle,Power Down

None

 

H

X

 

X

L

 

X

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

Deselect Cycle,Power Down

None

 

L

L

 

X

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

 

Deselect Cycle,Power Down

None

 

L

X

 

H

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

 

Deselect Cycle,Power Down

None

 

L

L

 

X

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

Deselect Cycle,Power Down

None

 

L

X

 

H

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

Snooze Mode,Power Down

None

 

X

X

 

X

H

 

X

 

X

 

X

 

 

X

 

X

 

X

Tri-State

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

X

 

X

 

 

X

 

L

 

L-H

Q

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

X

 

X

 

 

X

 

H

 

L-H

Tri-State

 

WRITE Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

L

 

X

 

L-H

D

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

H

 

L

 

L-H

Q

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

H

 

H

 

L-H

Tri-State

 

READ Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

H

 

L

 

L-H

Q

 

READ Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

 

READ Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

H

 

L

 

L-H

Q

Document #: 38-05237 Rev. *D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Page 13 of 36

[+] Feedback

Page 12 Page 14
Image 13
Page 12 Page 14
Contents Functional Description1 FeaturesSelection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz UnitLogic Block Diagram CY7C1382C 1M x Logic Block Diagram CY7C1380C 512K xCY7C1380C 512K X Pin ConfigurationsCY7C1382C 1M x CY7C1382C 512K x NC / 72M NC / 36MNC / 72M NC / 288MTqfp BGA CY7C1380C-Pin DefinitionsAddress Strobe from Processor, sampled Power supply inputs to the core of the deOn the rising edge of CLK, active LOW. When Address Strobe from Controller, sampled onSelects Burst Order . When tied to GND Power supply for the I/O circuitryGround for the I/O circuitry Serial data-out to the Jtag circuit . DeliversCY7C1382CPin Definitions ZZ sleep Input, active High . When asserted Rising edge of CLK, active LOW . When assertedPower supply inputs to the core of the device Address Strobe from Processor, sampled onSerial data-out to the Jtag circuit . Delivers data Functional Overview Single Read AccessesZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDAddress CE2 Adsp Adsc ADV Write CLKCLK Adsp Adsc ADV Write Truth Table for Read/Write5Function CY7C1380C BWEIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramBoundary Scan Register Bypass RegisterIdentification ID Register TAP Instruction SetTAP Timing TAP AC Switching Characteristics Over the operating Range95V TAP AC Output Load Equivalent 3V TAP AC Test ConditionsParameter Description Test Conditions MIN MAX Units Scan Register Sizes Identification Register DefinitionsIdentification Codes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x A10 Ball fBGA Boundary Scan Order CY7C1380C 512K xF10 G10 J10Ball fBGA Boundary Scan Order CY7C1382C 1M x Maximum Ratings Electrical Characteristics Over the Operating Range12Operating Range Ambient RangeCapacitance Thermal Resistance14Parameter Description Test Conditions FBGA Unit3V I/O Test Load AC Test Loads and Waveforms5V I/O Test Load Min Max Unit Switching Characteristics Over the Operating Range19Read Cycle Timing21 Switching WaveformsWrite Cycle Timing21 CLZ Read/Write Cycle Timing21, 23ZZ Mode Timing 25 CY7C1382C-250AC CY7C1380C-250BGC Ordering InformationCY7C1382C-167AI CY7C1380C-167BGI Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package DiagramsLead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams Document History Issue Date Orig. Description of ChangeREV ECN no
Top Page Image Contents