Cypress CY7C1482V25 manual TAP Timing, TAP AC Switching Characteristics Over the Operating Range9

CY7C1480V25

CY7C1482V25

CY7C1486V25

The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls.

Note that because the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

1	2
Test Clock
(TCK)	tTH
tTMSS	tTMSH
Test Mode Select
(TMS)
tTDIS	tTDIH
Test Data-In
(TDI)

3 4 5 6

tTL tCYC

tTDOV

tTDOX

Test Data-Out (TDO)

DON’T CARE UNDEFINED

TAP AC Switching Characteristics Over the Operating Range[9, 10]

Parameter	Description	Min	Max	Unit
Clock
tTCYC	TCK Clock Cycle Time	50		ns
tTF	TCK Clock Frequency		20	MHz
tTH	TCK Clock HIGH time	20		ns
tTL	TCK Clock LOW time	20		ns
Output Times
tTDOV	TCK Clock LOW to TDO Valid		10	ns
tTDOX	TCK Clock LOW to TDO Invalid	0		ns
Setup Times
tTMSS	TMS Setup to TCK Clock Rise	5		ns
tTDIS	TDI Setup to TCK Clock Rise	5		ns
tCS	Capture Setup to TCK Rise	5		ns
Hold Times
tTMSH	TMS Hold after TCK Clock Rise	5		ns
tTDIH	TDI Hold after Clock Rise	5		ns
tCH	Capture Hold after Clock Rise	5		ns

Notes

9.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

10.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Document #: 38-05282 Rev. *H Page 14 of 32

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