Cypress CY7C1486V25 Pin Configurations Pin Tqfp Pinout, CY7C1480V25 2M x, CY7C1482V25 4M x

Page 4

CY7C1480V25

CY7C1482V25

CY7C1486V25

Pin Configurations

100-Pin TQFP Pinout

DQPC

DQC

DQc

VDDQ

VSSQ

DQC

DQC

DQC

DQC

VSSQ

VDDQ

DQC

DQC

NC

VDD

NC

VSS

DQD

DQD

VDDQ

VSSQ

DQD

DQD

DQD

DQD

VSSQ

VDDQ

DQD DQD DQPD

	A A CE CE								BWD BWC BWB BWA CE V V CLK GW																			BWE OE				ADSC		ADSP		ADV A A
1 2																		3 DD SS
																		3 DD SS



100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1																														80
2																														79
3																														78
4																														77
5																														76
6																														75
7																														74
8																														73
9																														72
10																														71
11																														70
12																														69
13																														68
14																														67
15													CY7C1480V25																	66
16													CY7C1480V25																	65
17																(2M x 36)														64
18																														63
19																														62
20																														61
21																														60
22																														59
23																														58
24																														57
25																														56
26																														55
27																														54
28																														53
29																														52
30																														51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DQPB	NC
DQB	NC
DQB	NC
VDDQ	V
VSSQ	DDQ
VSSQ	V
DQB	SSQ
DQB	NC
DQB	NC
DQB	DQB
DQB	DQB
VSSQ	V
VDDQ	SSQ
VDDQ	V
DQB	DDQ
DQB	DQB
DQB	DQB
VSS	NC
NC	VDD
VDD	NC
ZZ	VSS
DQA	DQB
DQA	DQB
VDDQ	V
VSSQ	DDQ
VSSQ	V
DQA	SSQ
DQA	DQB
DQA	DQB
DQA	DQPB
DQA	NC
VSSQ	V
VDDQ	SSQ
VDDQ	V
DQA	DDQ
DQA	NC
DQA	NC
DQPA	NC

	A A CE						CE		NC NC BWB BWA CE V V CLK GW																		BWE OE				ADSC			ADSP	ADV A A
	1						2										3 DD SS
																	3 DD SS



	100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
	1																												80
	2																												79
	3																												78
	4																												77
	5																												76
	6																												75
	7																												74
	8																												73
	9																												72
	10																												71
	11																												70
	12																												69
	13																												68
	14												CY7C1482V25																67
	15												CY7C1482V25																66
	16															(4M x 18)													65
	17															(4M x 18)													64
	17																												64
	18																												63
	19																												62
	20																												61
	21																												60
	22																												59
	23																												58
	24																												57
	25																												56
	26																												55
	27																												54
	28																												53
	29																												52
	30																												51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A

NC

NC

VDDQ VSSQ

NC DQPA DQA DQA

VSSQ VDDQ

DQA DQA VSS NC VDD ZZ DQA

DQA

VDDQ

VSSQ

DQA DQA NC NC

VSSQ VDDQ

NC

NC

NC

1 0	SS DD
MODE A A A A A A	A A V V	A A A A A A A A A

1 0	SS DD
MODE A A A A A A	A A V V	A A A A A A A A A

Document #: 38-05282 Rev. *H

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Contents Features Functional Description1Selection Guide 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1480V25 2M x Logic Block Diagram CY7C1482V25 4M xLogic Block Diagram CY7C1486V25 1M x CLRCY7C1480V25 2M x Pin Configurations Pin Tqfp PinoutCY7C1482V25 4M x CY7C1482V25 4M x DQ G DQ B DQ GDQ B DQP G DQP C DQP F DQP B DQ CPin Definitions Single Read Accesses Single Write Accesses Initiated by AdspFunctional Overview TDILinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Truth Table Operation Add. UsedTruth Table for Read/Write FunctionTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Instruction Register TAP Instruction SetTAP AC Switching Characteristics Over the Operating Range9 TAP TimingParameter Description Min Max Unit Clock Output TimesTAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test Conditions8V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Codes Scan Register SizesBoundary Scan Exit Order 2M x Boundary Scan Exit Order 4M x A11 A10P10 M10Boundary Scan Exit Order 1M x Electrical Characteristics Over the Operating Range12 Maximum RatingsOperating Range Range AmbientThermal Resistance14 Capacitance14AC Test Loads and Waveforms Setup Times Switching Characteristics Over the Operating Range15Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Switching Waveforms Read Cycle Timing21Write Cycle Timing21 Read/Write Cycle Timing21, 23 ZZ Mode Timing25 DON’T CareOrdering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Date Orig. Description of ChangeDocument Number VKN/KKVTMP