Cypress CY7C1480V25 Document History, Document Number, Issue Date Orig. Description of Change

Page 31

CY7C1480V25

CY7C1482V25

CY7C1486V25

Document History Page

 

Document Title: CY7C1480V25/CY7C1482V25/CY7C1486V25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

 

Document Number: 38-05282

 

 

 

 

 

 

 

 

 

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

 

Change

 

 

 

 

 

 

**

114670

08/06/02

PKS

New Data Sheet

 

 

 

 

 

 

 

*A

118281

01/21/03

HGK

Changed tCO from 2.4 to 2.6 ns for 250 MHz

 

 

 

 

 

Updated features on page 1 for package offering

 

 

 

 

 

Removed 300 MHz offering

 

 

 

 

 

Updated Ordering Information

 

 

 

 

 

Changed Advanced Information to Preliminary

 

*B

233368

See ECN

NJY

Changed timing diagrams

 

 

 

 

 

Changed logic block diagrams

 

 

 

 

 

Modified Functional Description

 

 

 

 

 

Modified “Functional Overview” section

 

 

 

 

 

Added boundary scan order for all packages

 

 

 

 

 

Included thermal numbers and capacitance values for all packages

 

 

 

 

 

Included IDD and ISB values

 

 

 

 

 

Removed 250-MHz speed grade offering and included 225 MHz speed bin

 

 

 

 

 

Changed package outline for 165FBGA package and 209-ball BGA package

 

 

 

 

 

Removed 119-BGA package offering

 

*C

299452

See ECN

SYT

Removed 225-MHz offering and included 250-MHz speed bin

 

 

 

 

 

Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin

 

 

 

 

 

Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100

 

 

 

 

 

TQFP Package on Page # 20

 

 

 

 

 

Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA

 

 

 

 

 

Packages

 

 

 

 

 

Added comment of ‘Lead-free BG packages availability’ below the Ordering

 

 

 

 

 

Information

 

*D

323039

See ECN

PCI

Unshaded 200 and 167 MHz speed bin in the AC/DC Table and Selection

 

 

 

 

 

Guide

 

 

 

 

 

Address expansion pins/balls in the pinouts for all packages are modified as

 

 

 

 

 

per JEDEC standard

 

 

 

 

 

Added Address Expansion pins in the Pin Definitions Table

 

 

 

 

 

Added Truth Table and Note# 7 for CY7C1486V25 on page# 11

 

 

 

 

 

Modified VOL, VOH Test Conditions

 

 

 

 

 

Added Industrial temperature range

 

 

 

 

 

Removed comment of ‘Lead-free BG packages availability’ below the

 

 

 

 

 

Ordering Information

 

 

 

 

 

Updated Ordering Information Table

 

*E

416193

See ECN

NXR

Converted from Preliminary to Final

 

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage

 

 

 

 

 

Current on page# 19

 

 

 

 

 

Changed the IX current values of MODE on page # 19 from -5 ∝A and 30 ∝A

 

 

 

 

 

to -30 ∝A and 5 ∝A

 

 

 

 

 

Changed the IX current values of ZZ on page # 19 from -30 ∝A and 5 ∝A

 

 

 

 

 

to -5 ∝A and 30 ∝A

 

 

 

 

 

Changed VIH < VDD to VIH < VDD on page # 19

 

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

 

Information table

 

 

 

 

 

Updated the Ordering Information Table

 

*F

470723

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

 

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

 

 

 

 

 

AC Switching Characteristics table

 

 

 

 

 

Updated the Ordering Information table

Document #: 38-05282 Rev. *H

 

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Contents 250 MHz 200 MHz 167 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1482V25 4M x Logic Block Diagram CY7C1480V25 2M xCLR Logic Block Diagram CY7C1486V25 1M xCY7C1480V25 2M x Pin Configurations Pin Tqfp PinoutCY7C1482V25 4M x CY7C1482V25 4M x DQP F DQP B DQ C DQ G DQ BDQ G DQ B DQP G DQP CPin Definitions TDI Single Read AccessesSingle Write Accesses Initiated by Adsp Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Operation Add. Used Truth TableFunction Truth Table for Read/WriteTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Instruction RegisterOutput Times TAP AC Switching Characteristics Over the Operating Range9TAP Timing Parameter Description Min Max Unit ClockParameter Description Test Conditions Min TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions 8V TAP AC Test ConditionsIdentification Codes Scan Register SizesBoundary Scan Exit Order 2M x M10 Boundary Scan Exit Order 4M xA11 A10 P10Boundary Scan Exit Order 1M x Range Ambient Electrical Characteristics Over the Operating Range12Maximum Ratings Operating RangeThermal Resistance14 Capacitance14AC Test Loads and Waveforms Setup Times Switching Characteristics Over the Operating Range15Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Read Cycle Timing21 Switching WaveformsWrite Cycle Timing21 Read/Write Cycle Timing21, 23 DON’T Care ZZ Mode Timing25Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Date Orig. Description of ChangeDocument Number VKN/KKVTMP
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