Cypress CY7C1480V25, CY7C1486V25, CY7C1482V25 manual Truth Table, Operation Add. Used

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CY7C1480V25

CY7C1482V25

CY7C1486V25

Truth Table

The truth table for CY7C1480V25, CY7C1482V25, and CY7C1486V25 follows.[3, 4, 5, 6, 7]

Operation

Add. Used

CE1

CE2

CE3

ZZ

ADSP

ADSC

ADV

WRITE

OE

CLK

DQ

Deselect Cycle, Power Down

None

H

X

X

L

X

L

X

X

X

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

L

L

X

L

L

X

X

X

X

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

L

X

H

L

L

X

X

X

X

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

L

L

X

L

H

L

X

X

X

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

L

X

H

L

H

L

X

X

X

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode, Power Down

None

X

X

X

H

X

X

X

X

X

X

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

L

H

L

L

L

X

X

X

L

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

L

H

L

L

L

X

X

X

H

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Begin Burst

External

L

H

L

L

H

L

X

L

X

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

L

H

L

L

H

L

X

H

L

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

L

H

L

L

H

L

X

H

H

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

L

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

H

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

L

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

H

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

X

X

X

L

H

H

L

L

X

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

H

X

X

L

X

H

L

L

X

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

L

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

H

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

L

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

H

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

L

X

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

L

X

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

3.X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

4.WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.

5.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6.The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to enable the outputs to tri-state. OE is a don't care for the remainder of the write cycle

7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 38-05282 Rev. *H

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Contents Selection Guide FeaturesFunctional Description1 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1480V25 2M x Logic Block Diagram CY7C1482V25 4M xLogic Block Diagram CY7C1486V25 1M x CLRCY7C1480V25 2M x Pin Configurations Pin Tqfp PinoutCY7C1482V25 4M x CY7C1482V25 4M x DQ B DQP G DQP C DQ G DQ BDQ G DQP F DQP B DQ CPin Definitions Functional Overview Single Read AccessesSingle Write Accesses Initiated by Adsp TDILinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Truth Table Operation Add. UsedTruth Table for Read/Write FunctionTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Instruction Register TAP Instruction SetParameter Description Min Max Unit Clock TAP AC Switching Characteristics Over the Operating Range9TAP Timing Output Times8V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Codes Scan Register SizesBoundary Scan Exit Order 2M x P10 Boundary Scan Exit Order 4M xA11 A10 M10Boundary Scan Exit Order 1M x Operating Range Electrical Characteristics Over the Operating Range12Maximum Ratings Range AmbientThermal Resistance14 Capacitance14AC Test Loads and Waveforms Setup Times Switching Characteristics Over the Operating Range15Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Switching Waveforms Read Cycle Timing21Write Cycle Timing21 Read/Write Cycle Timing21, 23 ZZ Mode Timing25 DON’T CareOrdering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Date Orig. Description of ChangeDocument Number VKN/KKVTMP
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