Cypress CY7C1482V25, CY7C1486V25, CY7C1480V25 manual Truth Table for Read/Write, Function

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CY7C1480V25

CY7C1482V25

CY7C1486V25

Truth Table for Read/Write

The read/write truth table for the CY7C1480V25 follows.[5]

Function	GW	BWE	BWD	BWC	BWB	BWA
Read	H	H	X	X	X	X

Read	H	L	H	H	H	H

Write Byte A – (DQA and DQPA)	H	L	H	H	H	L
Write Byte B – (DQB and DQPB)	H	L	H	H	L	H
Write Bytes B, A	H	L	H	H	L	L

Write Byte C – (DQC and DQPC)	H	L	H	L	H	H
Write Bytes C, A	H	L	H	L	H	L

Write Bytes C, B	H	L	H	L	L	H

Write Bytes C, B, A	H	L	H	L	L	L

Write Byte D – (DQD and DQPD)	H	L	L	H	H	H
Write Bytes D, A	H	L	L	H	H	L

Write Bytes D, B	H	L	L	H	L	H

Write Bytes D, B, A	H	L	L	H	L	L

Write Bytes D, C	H	L	L	L	H	H

Write Bytes D, C, A	H	L	L	L	H	L

Write Bytes D, C, B	H	L	L	L	L	H

Write All Bytes	H	L	L	L	L	L

Write All Bytes	L	X	X	X	X	X

Truth Table for Read/Write

The read/write truth table for the CY7C1482V25 follows.[5]

Function

GW

BWE

BW

B

BW

A

Read

H

H

X

X

Read

H

L

H

H

Write Byte A – (DQA and DQPA)

H

L

H

L

Write Byte B – (DQB and DQPB)

H

L

L

H

Write Bytes B, A

H

L

L

L

Write All Bytes

H

L

L

L

Write All Bytes

L

X

X

X

Truth Table for Read/Write

The read/write truth table for the CY7C1486V25 follows.[8]

Function	GW			BWE	BWX
Read	H			H			X

Read	H			L	All	BW			= H
Write Byte x – (DQx and DQPx)	H			L			L

Write All Bytes	H			L	All		BW		= L

Write All Bytes	L			X			X

Note

8.BWx represents any byte write signal BW[0..7]. To enable any byte write BWx, a Logic LOW signal must be applied at clock rise. Any number of byte writes can be enabled at the same time for any given write.

Document #: 38-05282 Rev. *H

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Contents 250 MHz 200 MHz 167 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1482V25 4M x Logic Block Diagram CY7C1480V25 2M xCLR Logic Block Diagram CY7C1486V25 1M xCY7C1482V25 4M x Pin Configurations Pin Tqfp PinoutCY7C1480V25 2M x CY7C1482V25 4M x DQP F DQP B DQ C DQ G DQ BDQ G DQ B DQP G DQP CPin Definitions TDI Single Read AccessesSingle Write Accesses Initiated by Adsp Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Operation Add. Used Truth TableFunction Truth Table for Read/WriteIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Instruction RegisterOutput Times TAP AC Switching Characteristics Over the Operating Range9TAP Timing Parameter Description Min Max Unit ClockParameter Description Test Conditions Min TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions 8V TAP AC Test ConditionsBoundary Scan Exit Order 2M x Scan Register SizesIdentification Codes M10 Boundary Scan Exit Order 4M xA11 A10 P10Boundary Scan Exit Order 1M x Range Ambient Electrical Characteristics Over the Operating Range12Maximum Ratings Operating RangeAC Test Loads and Waveforms Capacitance14Thermal Resistance14 Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Switching Characteristics Over the Operating Range15Setup Times Read Cycle Timing21 Switching WaveformsWrite Cycle Timing21 Read/Write Cycle Timing21, 23 DON’T Care ZZ Mode Timing25Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document Number Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP