Cypress CY7C1482V25, CY7C1486V25, CY7C1480V25 manual Write Cycle Timing21

Page 23

CY7C1480V25

CY7C1482V25

CY7C1486V25

Switching Waveforms (continued)

Write Cycle Timing[21, 22]

 

 

t CYC

 

 

 

 

 

 

 

 

 

 

CLK

 

tCH

tCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tADS

tADH

 

 

 

 

 

 

 

 

 

 

 

ADSP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tADS

tADH

 

 

ADSC extends burst

 

 

 

 

 

 

 

 

 

 

tADS

tADH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADSC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

tAH

 

 

 

 

 

 

 

 

 

 

 

ADDRESS

 

A1

 

 

A2

 

 

 

 

A3

 

 

 

 

 

Byte

write signals

are

 

 

 

 

 

 

 

 

 

 

ignored for first cycle when

 

 

 

 

 

tWES

tWEH

 

 

 

ADSP initiates burst

 

 

 

 

 

 

BWE,

 

 

 

 

 

 

 

 

 

 

 

 

 

BW X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWES tWEH

 

 

 

 

 

 

 

GW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCES

tCEH

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tADVS

tADVH

 

ADV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADV suspends burst

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDS

tDH

 

 

 

 

 

 

 

 

Data In (D)

High-Z

t

D(A1)

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OEHZ

 

 

 

 

 

 

 

 

 

 

 

Data Out (Q)

 

 

 

 

 

 

 

 

 

 

 

 

 

BURST READ

Single WRITE

 

BURST WRITE

DON’T CARE

UNDEFINED

Extended BURST WRITE

Note

22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

Document #: 38-05282 Rev. *H

Page 23 of 32

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Contents 250 MHz 200 MHz 167 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1482V25 4M x Logic Block Diagram CY7C1480V25 2M xCLR Logic Block Diagram CY7C1486V25 1M xCY7C1482V25 4M x Pin Configurations Pin Tqfp PinoutCY7C1480V25 2M x CY7C1482V25 4M x DQP F DQP B DQ C DQ G DQ BDQ G DQ B DQP G DQP CPin Definitions TDI Single Read AccessesSingle Write Accesses Initiated by Adsp Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Operation Add. Used Truth TableFunction Truth Table for Read/WriteIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Instruction RegisterOutput Times TAP AC Switching Characteristics Over the Operating Range9TAP Timing Parameter Description Min Max Unit ClockParameter Description Test Conditions Min TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions 8V TAP AC Test ConditionsBoundary Scan Exit Order 2M x Scan Register SizesIdentification Codes M10 Boundary Scan Exit Order 4M xA11 A10 P10Boundary Scan Exit Order 1M x Range Ambient Electrical Characteristics Over the Operating Range12Maximum Ratings Operating RangeAC Test Loads and Waveforms Capacitance14Thermal Resistance14 Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Switching Characteristics Over the Operating Range15Setup Times Read Cycle Timing21 Switching WaveformsWrite Cycle Timing21 Read/Write Cycle Timing21, 23 DON’T Care ZZ Mode Timing25Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document Number Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP