Cypress CY7C1464AV25 manual TAP Timing, Parameter Description Min Max Unit Clock, Output Times

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value

loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

12

Test Clock

(TCK)tTH

tTMSS tTMSH

Test Mode Select (TMS)

tTDIS tTDIH

Test Data-In (TDI)

3

4

5

6

tTL tCYC

tTDOV

tTDOX

 

Test Data-Out

 

 

 

 

(TDO)

 

 

 

 

DON’T CARE

UNDEFINED

 

 

TAP AC Switching Characteristics Over the Operating Range[9, 10]

 

 

 

Parameter

Description

Min.

Max.

Unit

Clock

 

 

 

 

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH time

20

 

ns

tTL

TCK Clock LOW time

20

 

ns

Output Times

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

Set-up Times

 

 

 

tTMSS

TMS Set-up to TCK Clock Rise

5

 

ns

tTDIS

TDI Set-up to TCK Clock Rise

5

 

ns

tCS

Capture Set-up to TCK Rise

5

 

ns

Hold Times

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Notes:

9.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.

Document #: 38-05354 Rev. *D

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Contents Features Logic Block Diagram-CY7C1460AV25 1M xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1462AV25 2M x Logic Block Diagram-CY7C1464AV25 512K xSelection Guide 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV25 2M × Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active LOW. Qualified with ADV/LDPower supply inputs to the core of the device Power supply for the I/O circuitryType Pin Description Clock input to the Jtag circuitrySingle Read Accesses Burst Read AccessesSingle Write Accesses Burst Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Partial Write Cycle Description1, 2, 3 Function CY7C1460AV25 BW d BW c BW b BW aFunction CY7C1462AV25 Function CY7C1464AV25TAP Controller Block Diagram TAP Controller State Diagram Disabling the Jtag FeatureTest Access Port TAP Performing a TAP ResetBypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test Conditions8V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size Instruction Code DescriptionBall Fbga Boundary Scan Order12 CY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball IDBit# Ball ID Ball Fbga Boundary Scan Order 12 CY7C1464AV25 512K x Bit# Ball IDElectrical Characteristics Over the Operating Range14 Maximum RatingsOperating Range Ambient RangeCapacitance16 Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range 21 250 200 167 Parameter Description Unit Min MaxSwitching Waveforms Read/Write/Timing23, 24NOP, Stall and Deselect Cycles23, 24 ZZ Mode Timing27 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document HistorySYT RXU

CY7C1462AV25, CY7C1460AV25, CY7C1464AV25 specifications

The Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 are a family of high-performance synchronous SRAM devices that have been designed for applications requiring fast memory access and low latency. These memory chips are particularly appealing for systems in telecommunications, networking, and embedded applications due to their versatility and robust performance specifications.

One of the standout features of the CY7C1464AV25 series is their large capacities. The CY7C1464AV25 offers a capacity of 4 Megabits (512 K x 8), making it well-suited for applications that demand ample memory while maintaining high-speed operations. In contrast, the CY7C1460AV25 and CY7C1462AV25 provide slightly smaller capacities of 1 Megabit (128 K x 8) and 2 Megabits (256 K x 8) respectively, catering to varying system memory requirements.

All three devices utilize Cypress's advanced synchronous SRAM technology. This enables the chips to support burst read and write modes, allowing for rapid data transfer rates. The CY7C1464AV25 delivers a data access time of as low as 5.5 ns, making it highly efficient for data-intensive applications. Additionally, the standard operating voltage of 2.5V aids in reducing power consumption and improving overall system energy efficiency.

The chips are also characterized by a simple interface and compatibility with common bus protocols, which facilitates easy integration into existing systems. They feature a dual-port architecture, allowing multiple data transfers to occur simultaneously, significantly improving throughput.

With a commercial temperature range, all three devices offer reliability and are suited for a wide range of operating environments. The package options include a compact 44-pin TSOP, allowing for space-saving designs in modern electronics.

In summary, the Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 provide a powerful blend of capacity, speed, and efficiency, making them ideal choices for demanding applications in various sectors. Their advanced technologies and versatility make them excellent candidates for enhancing system performance while maintaining low power consumption and ensuring reliable operation in various conditions.
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