Cypress CY7C1464AV25, CY7C1462AV25 manual Type Pin Description, Clock input to the Jtag circuitry

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CY7C1460AV25

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1462AV25

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1464AV25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

Pin Name

I/O Type

 

 

Pin Description

 

 

 

 

 

1

 

Input-

 

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

 

 

 

CE

 

 

 

 

 

 

 

 

Synchronous

 

CE2 and CE3 to select/deselect the device.

 

 

 

CE2

Input-

 

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

 

 

 

 

 

 

 

 

Synchronous

 

CE1 and CE3 to select/deselect the device.

 

 

 

 

 

3

 

Input-

 

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

 

 

 

CE

 

 

 

 

 

 

 

 

Synchronous

 

CE1 and CE2 to select/deselect the device.

 

 

 

 

 

 

 

 

Input-

 

Output Enable, active LOW. Combined with the synchronous logic block inside the device to

 

 

 

 

OE

 

 

 

 

 

 

 

 

Asynchronous

 

control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.

 

 

 

 

 

 

 

 

 

 

 

 

When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during

 

 

 

 

 

 

 

 

 

 

 

 

the data portion of a write sequence, during the first clock when emerging from a deselected state

 

 

 

 

 

 

 

 

 

 

 

 

and when the device has been deselected.

 

 

 

 

 

 

 

 

Input-

 

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the

 

 

CEN

 

 

 

 

 

 

 

 

Synchronous

 

SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not

 

 

 

 

 

 

 

 

 

 

 

 

deselect the device, CEN can be used to extend the previous cycle when required.

 

 

DQa

I/O-

 

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

 

 

DQb

Synchronous

 

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

 

 

DQc

 

 

 

 

specified by AX

during the previous clock rise of the read cycle. The direction of the pins is

 

 

DQd

 

 

 

 

controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave

 

 

DQe

 

 

 

 

as outputs. When HIGH, DQa–DQdare placed in a tri-state condition. The outputs are automati-

 

 

 

DQf

 

 

 

 

cally tri-stated during the data portion of a write sequence, during the first clock when emerging

 

 

DQg

 

 

 

 

from a deselected state, and when the device is deselected, regardless of the state of OE.

 

 

DQh

 

 

 

 

 

 

 

 

DQPa

I/O-

 

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During

 

DQPb

Synchronous

 

write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by

 

DQPc

 

 

 

 

BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf,

 

DQPd

 

 

 

 

DQPg is controlled by BWg, DQPh is controlled by BWh.

 

DQPe

 

 

 

 

 

 

 

 

DQPf

 

 

 

 

 

 

 

 

DQPg

 

 

 

 

 

 

 

 

DQPh

 

 

 

 

 

 

 

 

MODE

Input Strap Pin

 

Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

 

 

 

 

 

 

 

 

 

 

 

 

Pulled LOW selects the linear burst order. MODE should not change states during operation.

 

 

 

 

 

 

 

 

 

 

 

 

When left floating MODE will default HIGH, to an interleaved burst order.

 

 

TDO

JTAG serial output

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

 

 

 

 

 

 

 

 

Synchronous

 

 

 

 

 

 

 

TDI

JTAG serial input

 

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

 

 

 

 

 

 

 

 

Synchronous

 

 

 

 

 

 

TMS

Test Mode Select

 

This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

 

 

 

 

 

 

 

 

Synchronous

 

 

 

 

 

 

TCK

JTAG-Clock

 

Clock input to the JTAG circuitry.

 

 

 

VDD

Power Supply

 

Power supply inputs to the core of the device.

 

VDDQ

I/O Power Supply

 

Power supply for the I/O circuitry.

 

 

 

VSS

Ground

 

Ground for the device. Should be connected to ground of the system.

 

 

 

 

NC

N/A

 

No connects. This pin is not connected to the die.

 

NC/72M

N/A

 

Not connected to the die. Can be tied to any voltage level.

 

NC/144M

N/A

 

Not connected to the die. Can be tied to any voltage level.

 

NC/288M

N/A

 

Not connected to the die. Can be tied to any voltage level.

 

NC/576M

N/A

 

Not connected to the die. Can be tied to any voltage level.

 

NC/1G

N/A

 

Not connected to the die. Can be tied to any voltage level.

 

 

 

 

ZZ

Input-

 

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

 

 

 

 

 

 

 

 

Asynchronous

 

with data integrity preserved. During normal operation, this pin has to be LOW or left floating.

 

 

 

 

 

 

 

 

 

 

 

 

ZZ pin has an internal pull-down.

Document #: 38-05354 Rev. *D

 

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1460AV25 1M x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1462AV25 2M xLogic Block Diagram-CY7C1464AV25 512K x 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV25 2M × Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsPin Name Type Pin Description ADV/LDType Pin Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Clock input to the Jtag circuitrySingle Write Accesses Single Read AccessesBurst Read Accesses Burst Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1462AV25 Partial Write Cycle Description1, 2, 3Function CY7C1460AV25 BW d BW c BW b BW a Function CY7C1464AV25Test Access Port TAP TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Performing a TAP ResetBypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times8V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBall Fbga Boundary Scan Order12 CY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball IDBit# Ball ID Ball Fbga Boundary Scan Order 12 CY7C1464AV25 512K x Bit# Ball IDOperating Range Electrical Characteristics Over the Operating Range14Maximum Ratings Ambient RangeCapacitance16 Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range 21 250 200 167 Parameter Description Unit Min MaxSwitching Waveforms Read/Write/Timing23, 24NOP, Stall and Deselect Cycles23, 24 ZZ Mode Timing27 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm SYT ECN No Issue Date Orig. Description of ChangeDocument History RXU

CY7C1462AV25, CY7C1460AV25, CY7C1464AV25 specifications

The Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 are a family of high-performance synchronous SRAM devices that have been designed for applications requiring fast memory access and low latency. These memory chips are particularly appealing for systems in telecommunications, networking, and embedded applications due to their versatility and robust performance specifications.

One of the standout features of the CY7C1464AV25 series is their large capacities. The CY7C1464AV25 offers a capacity of 4 Megabits (512 K x 8), making it well-suited for applications that demand ample memory while maintaining high-speed operations. In contrast, the CY7C1460AV25 and CY7C1462AV25 provide slightly smaller capacities of 1 Megabit (128 K x 8) and 2 Megabits (256 K x 8) respectively, catering to varying system memory requirements.

All three devices utilize Cypress's advanced synchronous SRAM technology. This enables the chips to support burst read and write modes, allowing for rapid data transfer rates. The CY7C1464AV25 delivers a data access time of as low as 5.5 ns, making it highly efficient for data-intensive applications. Additionally, the standard operating voltage of 2.5V aids in reducing power consumption and improving overall system energy efficiency.

The chips are also characterized by a simple interface and compatibility with common bus protocols, which facilitates easy integration into existing systems. They feature a dual-port architecture, allowing multiple data transfers to occur simultaneously, significantly improving throughput.

With a commercial temperature range, all three devices offer reliability and are suited for a wide range of operating environments. The package options include a compact 44-pin TSOP, allowing for space-saving designs in modern electronics.

In summary, the Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 provide a powerful blend of capacity, speed, and efficiency, making them ideal choices for demanding applications in various sectors. Their advanced technologies and versatility make them excellent candidates for enhancing system performance while maintaining low power consumption and ensuring reliable operation in various conditions.
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