Cypress CY7C1464AV25, CY7C1460AV25 Partial Write Cycle Description1, 2, 3, Function CY7C1462AV25

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Partial Write Cycle Description[1, 2, 3, 8]

Function (CY7C1460AV25)

 

WE

 

BWd

 

 

BWc

 

 

BWb

 

 

 

 

BWa

Read

 

H

 

X

 

 

 

X

 

 

X

 

 

 

 

 

 

 

X

Write – No bytes written

 

L

 

H

 

 

 

H

 

 

H

 

 

 

 

 

 

 

H

Write Byte a – (DQa and DQPa)

 

L

 

H

 

 

 

H

 

 

H

 

 

 

 

 

 

 

L

Write Byte b – (DQb and DQPb)

 

L

 

H

 

 

 

H

 

 

L

 

 

 

 

 

 

 

H

Write Bytes b, a

 

L

 

H

 

 

 

H

 

 

L

 

 

 

 

 

 

 

L

Write Byte c – (DQc and DQPc)

 

L

 

H

 

 

 

L

 

 

H

 

 

 

 

 

 

 

H

Write Bytes c, a

 

L

 

H

 

 

 

L

 

 

H

 

 

 

 

 

 

 

L

Write Bytes c, b

 

L

 

H

 

 

 

LL

 

 

L

 

 

 

 

 

 

 

H

Write Bytes c, b, a

 

L

 

H

 

 

 

L

 

 

L

 

 

 

 

 

 

 

L

Write Byte d – (DQd and DQPd)

 

L

 

L

 

 

 

H

 

 

H

 

 

 

 

 

 

 

H

Write Bytes d, a

 

L

 

L

 

 

 

H

 

 

H

 

 

 

 

 

 

 

L

Write Bytes d, b

 

L

 

L

 

 

 

H

 

 

L

 

 

 

 

 

 

 

H

Write Bytes d, b, a

 

L

 

L

 

 

 

H

 

 

L

 

 

 

 

 

 

 

L

Write Bytes d, c

 

L

 

L

 

 

 

L

 

 

H

 

 

 

 

 

 

 

H

Write Bytes d, c, a

 

L

 

L

 

 

 

L

 

 

H

 

 

 

 

 

 

 

L

Write Bytes d, c, b

 

L

 

L

 

 

 

L

 

 

L

 

 

 

 

 

 

 

H

Write All Bytes

 

L

 

L

 

 

 

L

 

 

L

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Function (CY7C1462AV25)

 

 

 

 

WE

 

 

 

 

 

 

BW

b

 

 

 

BW

a

Read

 

 

 

 

H

 

 

 

 

 

X

 

 

 

 

X

Write – No Bytes Written

 

 

 

 

L

 

 

 

 

 

H

 

 

 

 

H

Write Byte a – (DQa and DQPa)

 

 

 

 

L

 

 

 

 

 

H

 

 

 

 

L

Write Byte b – (DQb and DQPb)

 

 

 

 

L

 

 

 

 

 

 

L

 

 

 

 

H

Write Both Bytes

 

 

 

 

L

 

 

 

 

 

 

L

 

 

 

 

L

Function (CY7C1464AV25)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

BW

Read

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

X

Write – No Bytes Written

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

H

Write Byte X − (DQx and DQPx)

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

L

Write All Bytes

 

 

 

 

 

 

 

 

L

 

 

 

All

 

 

 

= L

 

 

 

 

 

 

 

 

 

 

 

BW

Note:

8. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.

Document #: 38-05354 Rev. *D

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Contents Logic Block Diagram-CY7C1460AV25 1M x FeaturesFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1464AV25 512K x Logic Block Diagram-CY7C1462AV25 2M xSelection Guide 250 MHz 200 MHz 167 MHz Unit2M × Pin Configurations Pin Tqfp PinoutCY7C1462AV25 2M × Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with ADV/LDPower supply for the I/O circuitry Power supply inputs to the core of the deviceType Pin Description Clock input to the Jtag circuitryBurst Read Accesses Single Read AccessesSingle Write Accesses Burst Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1460AV25 BW d BW c BW b BW a Partial Write Cycle Description1, 2, 3Function CY7C1462AV25 Function CY7C1464AV25Disabling the Jtag Feature TAP Controller Block Diagram TAP Controller State DiagramTest Access Port TAP Performing a TAP ResetTAP Instruction Set Bypass RegisterParameter Description Min Max Unit Clock TAP TimingOutput Times Set-up Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions8V TAP AC Test Conditions Identification Register DefinitionsIdentification Codes Scan Register SizesRegister Name Bit Size Instruction Code DescriptionBall Fbga Boundary Scan Order12 CY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball IDBit# Ball ID CY7C1464AV25 512K x Bit# Ball ID Ball Fbga Boundary Scan Order 12Maximum Ratings Electrical Characteristics Over the Operating Range14Operating Range Ambient RangeCapacitance16 Thermal ResistanceAC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 21Switching Waveforms Read/Write/Timing23, 24NOP, Stall and Deselect Cycles23, 24 DON’T Care ZZ Mode Timing27Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of ChangeSYT RXU

CY7C1462AV25, CY7C1460AV25, CY7C1464AV25 specifications

The Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 are a family of high-performance synchronous SRAM devices that have been designed for applications requiring fast memory access and low latency. These memory chips are particularly appealing for systems in telecommunications, networking, and embedded applications due to their versatility and robust performance specifications.

One of the standout features of the CY7C1464AV25 series is their large capacities. The CY7C1464AV25 offers a capacity of 4 Megabits (512 K x 8), making it well-suited for applications that demand ample memory while maintaining high-speed operations. In contrast, the CY7C1460AV25 and CY7C1462AV25 provide slightly smaller capacities of 1 Megabit (128 K x 8) and 2 Megabits (256 K x 8) respectively, catering to varying system memory requirements.

All three devices utilize Cypress's advanced synchronous SRAM technology. This enables the chips to support burst read and write modes, allowing for rapid data transfer rates. The CY7C1464AV25 delivers a data access time of as low as 5.5 ns, making it highly efficient for data-intensive applications. Additionally, the standard operating voltage of 2.5V aids in reducing power consumption and improving overall system energy efficiency.

The chips are also characterized by a simple interface and compatibility with common bus protocols, which facilitates easy integration into existing systems. They feature a dual-port architecture, allowing multiple data transfers to occur simultaneously, significantly improving throughput.

With a commercial temperature range, all three devices offer reliability and are suited for a wide range of operating environments. The package options include a compact 44-pin TSOP, allowing for space-saving designs in modern electronics.

In summary, the Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 provide a powerful blend of capacity, speed, and efficiency, making them ideal choices for demanding applications in various sectors. Their advanced technologies and versatility make them excellent candidates for enhancing system performance while maintaining low power consumption and ensuring reliable operation in various conditions.
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