Cypress CY7C1464AV25, CY7C1462AV25, CY7C1460AV25 Ball Fbga Boundary Scan Order12, Bit# Ball ID

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

165-ball FBGA Boundary Scan Order[12]

CY7C1460AV25 (1M x 36), CY7C1462AV25 (2M x 18)

Bit#	Ball ID	Bit#	Ball ID	Bit#	Ball ID
1	N6	26	E11	51	A3

2	N7	27	D11	52	A2

3	N10	28	G10	53	B2

4	P11	29	F10	54	C2

5	P8	30	E10	55	B1

6	R8	31	D10	56	A1

7	R9	32	C11	57	C1

8	P9	33	A11	58	D1

9	P10	34	B11	59	E1

10	R10	35	A10	60	F1

11	R11	36	B10	61	G1

12	H11	37	A9	62	D2

13	N11	38	B9	63	E2

14	M11	39	C10	64	F2

15	L11	40	A8	65	G2

16	K11	41	B8	66	H1

17	J11	42	A7	67	H3

18	M10	43	B7	68	J1

19	L10	44	B6	69	K1

20	K10	45	A6	70	L1

21	J10	46	B5	71	M1

22	H9	47	A5	72	J2

23	H10	48	A4	73	K2

24	G11	49	B4	74	L2

25	F11	50	B3	75	M2

Bit#

Ball ID

76N1

77N2

78P1

79R1

80R2

81P3

82R3

83P2

84R4

85P4

86N5

87P6

88R6

89Internal

Note:

12. Bit# 89 is preset HIGH.

Document #: 38-05354 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1460AV25 1M x Functional Description250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1462AV25 2M xLogic Block Diagram-CY7C1464AV25 512K x Selection Guide2M × Pin Configurations Pin Tqfp PinoutCY7C1462AV25 2M × ADV/LD Pin DefinitionsPin Name Type Pin Description Byte Write Select Inputs, active LOW. Qualified withClock input to the Jtag circuitry Power supply inputs to the core of the devicePower supply for the I/O circuitry Type Pin DescriptionBurst Write Accesses Single Read AccessesBurst Read Accesses Single Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1464AV25 Partial Write Cycle Description1, 2, 3Function CY7C1460AV25 BW d BW c BW b BW a Function CY7C1462AV25Performing a TAP Reset TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Test Access Port TAPTAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Description Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions 8V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeBall Fbga Boundary Scan Order12 CY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball IDBit# Ball ID CY7C1464AV25 512K x Bit# Ball ID Ball Fbga Boundary Scan Order 12Ambient Range Electrical Characteristics Over the Operating Range14Maximum Ratings Operating RangeCapacitance16 Thermal ResistanceAC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 21Switching Waveforms Read/Write/Timing23, 24NOP, Stall and Deselect Cycles23, 24 DON’T Care ZZ Mode Timing27Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm RXU ECN No Issue Date Orig. Description of ChangeDocument History SYT

CY7C1462AV25, CY7C1460AV25, CY7C1464AV25 specifications

The Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 are a family of high-performance synchronous SRAM devices that have been designed for applications requiring fast memory access and low latency. These memory chips are particularly appealing for systems in telecommunications, networking, and embedded applications due to their versatility and robust performance specifications.

One of the standout features of the CY7C1464AV25 series is their large capacities. The CY7C1464AV25 offers a capacity of 4 Megabits (512 K x 8), making it well-suited for applications that demand ample memory while maintaining high-speed operations. In contrast, the CY7C1460AV25 and CY7C1462AV25 provide slightly smaller capacities of 1 Megabit (128 K x 8) and 2 Megabits (256 K x 8) respectively, catering to varying system memory requirements.

All three devices utilize Cypress's advanced synchronous SRAM technology. This enables the chips to support burst read and write modes, allowing for rapid data transfer rates. The CY7C1464AV25 delivers a data access time of as low as 5.5 ns, making it highly efficient for data-intensive applications. Additionally, the standard operating voltage of 2.5V aids in reducing power consumption and improving overall system energy efficiency.

The chips are also characterized by a simple interface and compatibility with common bus protocols, which facilitates easy integration into existing systems. They feature a dual-port architecture, allowing multiple data transfers to occur simultaneously, significantly improving throughput.

With a commercial temperature range, all three devices offer reliability and are suited for a wide range of operating environments. The package options include a compact 44-pin TSOP, allowing for space-saving designs in modern electronics.

In summary, the Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 provide a powerful blend of capacity, speed, and efficiency, making them ideal choices for demanding applications in various sectors. Their advanced technologies and versatility make them excellent candidates for enhancing system performance while maintaining low power consumption and ensuring reliable operation in various conditions.