Cypress CY7C1462AV25 manual Ball Fbga Boundary Scan Order 12, CY7C1464AV25 512K x Bit# Ball ID

Page 16

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

209-ball FBGA Boundary Scan Order [12, 13]

CY7C1464AV25 (512K x 72)

 

 

 

 

 

 

 

 

 

Bit#

Ball ID

 

Bit#

Ball ID

 

Bit#

Ball ID

 

Bit#

Ball ID

1

W6

 

36

F6

 

71

H6

 

106

K3

 

 

 

 

 

 

 

 

 

 

 

2

V6

 

37

K8

 

72

C6

 

107

K4

 

 

 

 

 

 

 

 

 

 

 

3

U6

 

38

K9

 

73

B6

 

108

K6

 

 

 

 

 

 

 

 

 

 

 

4

W7

 

39

K10

 

74

A6

 

109

K2

 

 

 

 

 

 

 

 

 

 

 

5

V7

 

40

J11

 

75

A5

 

110

L2

 

 

 

 

 

 

 

 

 

 

 

6

U7

 

41

J10

 

76

B5

 

111

L1

 

 

 

 

 

 

 

 

 

 

 

7

T7

 

42

H11

 

77

C5

 

112

M2

 

 

 

 

 

 

 

 

 

 

 

8

V8

 

43

H10

 

78

D5

 

113

M1

 

 

 

 

 

 

 

 

 

 

 

9

U8

 

44

G11

 

79

D4

 

114

N2

 

 

 

 

 

 

 

 

 

 

 

10

T8

 

45

G10

 

80

C4

 

115

N1

 

 

 

 

 

 

 

 

 

 

 

11

V9

 

46

F11

 

81

A4

 

116

P2

 

 

 

 

 

 

 

 

 

 

 

12

U9

 

47

F10

 

82

B4

 

117

P1

 

 

 

 

 

 

 

 

 

 

 

13

P6

 

48

E10

 

83

C3

 

118

R2

 

 

 

 

 

 

 

 

 

 

 

14

W11

 

49

E11

 

84

B3

 

119

R1

 

 

 

 

 

 

 

 

 

 

 

15

W10

 

50

D11

 

85

A3

 

120

T2

 

 

 

 

 

 

 

 

 

 

 

16

V11

 

51

D10

 

86

A2

 

121

T1

 

 

 

 

 

 

 

 

 

 

 

17

V10

 

52

C11

 

87

A1

 

122

U2

 

 

 

 

 

 

 

 

 

 

 

18

U11

 

53

C10

 

88

B2

 

123

U1

 

 

 

 

 

 

 

 

 

 

 

19

U10

 

54

B11

 

89

B1

 

124

V2

 

 

 

 

 

 

 

 

 

 

 

20

T11

 

55

B10

 

90

C2

 

125

V1

 

 

 

 

 

 

 

 

 

 

 

21

T10

 

56

A11

 

91

C1

 

126

W2

 

 

 

 

 

 

 

 

 

 

 

22

R11

 

57

A10

 

92

D2

 

127

W1

 

 

 

 

 

 

 

 

 

 

 

23

R10

 

58

C9

 

93

D1

 

128

T6

 

 

 

 

 

 

 

 

 

 

 

24

P11

 

59

B9

 

94

E1

 

129

U3

 

 

 

 

 

 

 

 

 

 

 

25

P10

 

60

A9

 

95

E2

 

130

V3

 

 

 

 

 

 

 

 

 

 

 

26

N11

 

61

D8

 

96

F2

 

131

T4

 

 

 

 

 

 

 

 

 

 

 

27

N10

 

62

C8

 

97

F1

 

132

T5

 

 

 

 

 

 

 

 

 

 

 

28

M11

 

63

B8

 

98

G1

 

133

U4

 

 

 

 

 

 

 

 

 

 

 

29

M10

 

64

A8

 

99

G2

 

134

V4

 

 

 

 

 

 

 

 

 

 

 

30

L11

 

65

D7

 

100

H2

 

135

W5

 

 

 

 

 

 

 

 

 

 

 

31

L10

 

66

C7

 

101

H1

 

136

V5

 

 

 

 

 

 

 

 

 

 

 

32

K11

 

67

B7

 

102

J2

 

137

U5

 

 

 

 

 

 

 

 

 

 

 

33

M6

 

68

A7

 

103

J1

 

138

Internal

 

 

 

 

 

 

 

 

 

 

 

34

L6

 

69

D6

 

104

K1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

35

J6

 

70

G6

 

105

N6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

13. Bit# 138 is preset HIGH.

Document #: 38-05354 Rev. *D

Page 16 of 27

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Contents Features Logic Block Diagram-CY7C1460AV25 1M xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1462AV25 2M x Logic Block Diagram-CY7C1464AV25 512K xSelection Guide 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV25 2M × Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active LOW. Qualified with ADV/LDPower supply inputs to the core of the device Power supply for the I/O circuitryType Pin Description Clock input to the Jtag circuitrySingle Read Accesses Burst Read AccessesSingle Write Accesses Burst Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Partial Write Cycle Description1, 2, 3 Function CY7C1460AV25 BW d BW c BW b BW aFunction CY7C1462AV25 Function CY7C1464AV25TAP Controller Block Diagram TAP Controller State Diagram Disabling the Jtag FeatureTest Access Port TAP Performing a TAP ResetBypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test Conditions8V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size Instruction Code DescriptionCY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball ID Ball Fbga Boundary Scan Order12Bit# Ball ID Ball Fbga Boundary Scan Order 12 CY7C1464AV25 512K x Bit# Ball IDElectrical Characteristics Over the Operating Range14 Maximum RatingsOperating Range Ambient RangeThermal Resistance Capacitance16AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 21 250 200 167 Parameter Description Unit Min MaxRead/Write/Timing23, 24 Switching WaveformsNOP, Stall and Deselect Cycles23, 24 ZZ Mode Timing27 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document HistorySYT RXU

CY7C1462AV25, CY7C1460AV25, CY7C1464AV25 specifications

The Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 are a family of high-performance synchronous SRAM devices that have been designed for applications requiring fast memory access and low latency. These memory chips are particularly appealing for systems in telecommunications, networking, and embedded applications due to their versatility and robust performance specifications.

One of the standout features of the CY7C1464AV25 series is their large capacities. The CY7C1464AV25 offers a capacity of 4 Megabits (512 K x 8), making it well-suited for applications that demand ample memory while maintaining high-speed operations. In contrast, the CY7C1460AV25 and CY7C1462AV25 provide slightly smaller capacities of 1 Megabit (128 K x 8) and 2 Megabits (256 K x 8) respectively, catering to varying system memory requirements.

All three devices utilize Cypress's advanced synchronous SRAM technology. This enables the chips to support burst read and write modes, allowing for rapid data transfer rates. The CY7C1464AV25 delivers a data access time of as low as 5.5 ns, making it highly efficient for data-intensive applications. Additionally, the standard operating voltage of 2.5V aids in reducing power consumption and improving overall system energy efficiency.

The chips are also characterized by a simple interface and compatibility with common bus protocols, which facilitates easy integration into existing systems. They feature a dual-port architecture, allowing multiple data transfers to occur simultaneously, significantly improving throughput.

With a commercial temperature range, all three devices offer reliability and are suited for a wide range of operating environments. The package options include a compact 44-pin TSOP, allowing for space-saving designs in modern electronics.

In summary, the Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 provide a powerful blend of capacity, speed, and efficiency, making them ideal choices for demanding applications in various sectors. Their advanced technologies and versatility make them excellent candidates for enhancing system performance while maintaining low power consumption and ensuring reliable operation in various conditions.