Cypress CY7C1460AV25, CY7C1464AV25, CY7C1462AV25 manual Ball Fbga 14 x 22 x 1.76 mm

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Package Diagrams (continued)

209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)

51-85167-**

ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders.

Document #: 38-05354 Rev. *D

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© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1460AV25 1M x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1462AV25 2M xLogic Block Diagram-CY7C1464AV25 512K x 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV25 2M × Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsPin Name Type Pin Description ADV/LDType Pin Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Clock input to the Jtag circuitrySingle Write Accesses Single Read AccessesBurst Read Accesses Burst Write AccessesZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Function CY7C1462AV25 Partial Write Cycle Description1, 2, 3Function CY7C1460AV25 BW d BW c BW b BW a Function CY7C1464AV25Test Access Port TAP TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Performing a TAP ResetBypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times8V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBit# Ball ID Ball Fbga Boundary Scan Order12CY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball ID Ball Fbga Boundary Scan Order 12 CY7C1464AV25 512K x Bit# Ball IDOperating Range Electrical Characteristics Over the Operating Range14Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance16Thermal Resistance Switching Characteristics Over the Operating Range 21 250 200 167 Parameter Description Unit Min MaxNOP, Stall and Deselect Cycles23, 24 Switching WaveformsRead/Write/Timing23, 24 ZZ Mode Timing27 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm SYT ECN No Issue Date Orig. Description of ChangeDocument History RXU