Cypress CY7C1464AV25 Document History, ECN No Issue Date Orig. Description of Change, Syt, Rxu

Page 27

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Document History Page

Document Title: CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 36-Mbit (1-Mbit x 36/2-Mbit x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05354

REV.

ECN No.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

254911

See ECN

SYT

New data sheet

 

 

 

 

Part number changed from previous revision (new and old part number

 

 

 

 

differ by the letter “A”)

*A

303533

See ECN

SYT

Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209

 

 

 

 

FBGA on Page # 5

 

 

 

 

Changed the test condition from VDD = Min. to VDD = Max for VOL in the

 

 

 

 

Electrical Characteristics table

 

 

 

 

Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All

 

 

 

 

Packages on the Thermal Resistance Table

 

 

 

 

Changed IDD from 450, 400 & 350 mA to 435, 385 & 335 mA for 250, 200

 

 

 

 

and 167 Mhz respectively

 

 

 

 

Changed ISB1 from 190, 180 and 170 mA to 185 mA for 250, 200 and 167

 

 

 

 

Mhz respectively

 

 

 

 

Changed ISB2 from 80 mA to 100 mA for all frequencies

 

 

 

 

Changed ISB3 from 180, 170 & 160 mA to 160 mA for 250, 200 and 167

 

 

 

 

Mhz respectively

 

 

 

 

Changed ISB4 from 100 mA to 110 mA for all frequencies

 

 

 

 

Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for

 

 

 

 

TQFP Package

 

 

 

 

Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 Mhz

 

 

 

 

Speed Bin

 

 

 

 

Added lead-free information for 100 TQFP, 165 FBGA and 209 FBGA

 

 

 

 

packages

*B

331778

See ECN

SYT

Modified Address Expansion balls in the pinouts for 165 FBGA and 209

 

 

 

 

FBGA Package as per JEDEC standards and updated the Pin Definitions

 

 

 

 

accordingly

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165

 

 

 

 

FBGA Package

 

 

 

 

Added Industrial Temperature Grade

 

 

 

 

Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respec-

 

 

 

 

tively

 

 

 

 

Updated the Ordering Information by Shading and Unshading MPNs as per

 

 

 

 

availability

*C

417547

See ECN

RXU

Converted from Preliminary to Final

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Modified test condition from VDDQ < VDD to VDDQ ≤ VDD

 

 

 

 

Changed IX current value in MODE from –5 & 30 ∝A to –30 & 5 ∝A respec-

 

 

 

 

tively and also Changed IX current value in ZZ from –30 & 5 ∝A to –5 & 30

 

 

 

 

∝A respectively on page# 19

 

 

 

 

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in

 

 

 

 

the Electrical Characteristics Table

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table

 

 

 

 

Replaced Package Diagram of 51-85050 from *A to *B

*D

473650

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

 

 

 

 

AC Switching Characteristics table.

 

 

 

 

Updated the Ordering Information table.

Document #: 38-05354 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1460AV25 1M x Functional Description250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1462AV25 2M xLogic Block Diagram-CY7C1464AV25 512K x Selection Guide2M × Pin Configurations Pin Tqfp PinoutCY7C1462AV25 2M × ADV/LD Pin DefinitionsPin Name Type Pin Description Byte Write Select Inputs, active LOW. Qualified withClock input to the Jtag circuitry Power supply inputs to the core of the devicePower supply for the I/O circuitry Type Pin DescriptionBurst Write Accesses Single Read AccessesBurst Read Accesses Single Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1464AV25 Partial Write Cycle Description1, 2, 3Function CY7C1460AV25 BW d BW c BW b BW a Function CY7C1462AV25Performing a TAP Reset TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Test Access Port TAPTAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Description Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions 8V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeBall Fbga Boundary Scan Order12 CY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball IDBit# Ball ID CY7C1464AV25 512K x Bit# Ball ID Ball Fbga Boundary Scan Order 12Ambient Range Electrical Characteristics Over the Operating Range14Maximum Ratings Operating RangeCapacitance16 Thermal ResistanceAC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 21Switching Waveforms Read/Write/Timing23, 24NOP, Stall and Deselect Cycles23, 24 DON’T Care ZZ Mode Timing27Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm RXU ECN No Issue Date Orig. Description of ChangeDocument History SYT
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