Cypress CY7C1460AV25, CY7C1464AV25 manual Interleaved Burst Address Table Mode = Floating or VDD

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

CY7C1460AV25, BWa,b,c,d for CY7C1460AV25 and BWa,b for CY7C1462AV25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table (MODE = Floating or VDD)

First

Second

Third

Fourth

Address

Address

Address

Address

A1,A0

A1,A0

A1,A0

A1,A0

00

01

10

11

01

00

11

10

10

11

00

01

11

10

01

00

Linear Burst Address Table (MODE = GND)

First

Second

Third

Fourth

Address

Address

Address

Address

A1,A0

A1,A0

A1,A0

A1,A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

Description

 

 

 

Test Conditions

 

 

 

 

 

Min.

Max.

 

Unit

IDDZZ

Sleep mode standby current

 

 

ZZ > VDD − 0.2V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

100

 

mA

tZZS

Device operation to ZZ

 

 

ZZ > VDD − 0.2V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2tCYC

 

ns

tZZREC

ZZ recovery time

 

 

 

 

ZZ < 0.2V

 

 

 

 

 

 

 

 

 

 

2tCYC

 

 

 

ns

tZZI

ZZ active to sleep current

 

 

This parameter is sampled

 

 

 

 

 

 

 

 

 

2tCYC

 

ns

tRZZI

ZZ Inactive to exit sleep current

 

 

This parameter is sampled

 

 

 

 

 

0

 

 

 

 

ns

Truth Table[1, 2, 3, 4, 5, 6, 7]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

Used

 

CE

 

ZZ

ADV/LD

 

 

WE

 

BWx

 

OE

 

 

CEN

CLK

 

 

DQ

Deselect Cycle

 

None

 

H

L

L

 

 

X

 

X

 

 

X

 

 

L

L-H

 

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Continue Deselect Cycle

None

 

X

L

H

 

 

X

 

X

 

 

X

 

 

L

L-H

 

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle (Begin Burst)

External

 

L

L

L

 

 

H

 

X

 

 

L

 

 

L

L-H

Data Out (Q)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle (Continue Burst)

Next

 

X

L

H

 

 

X

 

X

 

 

L

 

 

L

L-H

Data Out (Q)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/Dummy Read (Begin Burst)

External

 

L

L

L

 

 

H

 

X

 

H

 

 

L

L-H

 

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dummy Read (Continue Burst)

Next

 

X

L

H

 

 

X

 

X

 

H

 

 

L

L-H

 

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle (Begin Burst)

External

 

L

L

L

 

 

L

 

L

 

 

X

 

 

L

L-H

Data In (D)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle (Continue Burst)

Next

 

X

L

H

 

 

X

 

L

 

 

X

 

 

L

L-H

Data In (D)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/WRITE ABORT (Begin Burst)

None

 

L

L

L

 

 

L

 

H

 

 

X

 

 

L

L-H

 

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE ABORT (Continue Burst)

Next

 

X

L

H

 

 

X

 

H

 

 

X

 

 

L

L-H

 

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IGNORE CLOCK EDGE (Stall)

Current

 

X

L

X

 

 

X

 

X

 

 

X

 

 

H

L-H

 

 

–

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep MODE

 

None

 

X

H

X

 

 

X

 

X

 

 

X

 

 

X

X

 

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2.Write is defined by WE and BWX. See Write Cycle Description table for details.

3.When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

4.The DQ and DQP pins are controlled by the current cycle and the OE signal.

5.CEN = H inserts wait states.

6.Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Three-state when OE is inactive or when the device is deselected, and DQs=data when OE is active.

Document #: 38-05354 Rev. *D

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Contents Features Logic Block Diagram-CY7C1460AV25 1M xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1462AV25 2M x Logic Block Diagram-CY7C1464AV25 512K xSelection Guide 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV25 2M × Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active LOW. Qualified with ADV/LDPower supply inputs to the core of the device Power supply for the I/O circuitryType Pin Description Clock input to the Jtag circuitrySingle Read Accesses Burst Read AccessesSingle Write Accesses Burst Write AccessesZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Partial Write Cycle Description1, 2, 3 Function CY7C1460AV25 BW d BW c BW b BW aFunction CY7C1462AV25 Function CY7C1464AV25TAP Controller Block Diagram TAP Controller State Diagram Disabling the Jtag FeatureTest Access Port TAP Performing a TAP ResetBypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test Conditions8V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size Instruction Code DescriptionBit# Ball ID Ball Fbga Boundary Scan Order12CY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball ID Ball Fbga Boundary Scan Order 12 CY7C1464AV25 512K x Bit# Ball IDElectrical Characteristics Over the Operating Range14 Maximum RatingsOperating Range Ambient RangeAC Test Loads and Waveforms Capacitance16Thermal Resistance Switching Characteristics Over the Operating Range 21 250 200 167 Parameter Description Unit Min MaxNOP, Stall and Deselect Cycles23, 24 Switching WaveformsRead/Write/Timing23, 24 ZZ Mode Timing27 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document HistorySYT RXU

CY7C1462AV25, CY7C1460AV25, CY7C1464AV25 specifications

The Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 are a family of high-performance synchronous SRAM devices that have been designed for applications requiring fast memory access and low latency. These memory chips are particularly appealing for systems in telecommunications, networking, and embedded applications due to their versatility and robust performance specifications.

One of the standout features of the CY7C1464AV25 series is their large capacities. The CY7C1464AV25 offers a capacity of 4 Megabits (512 K x 8), making it well-suited for applications that demand ample memory while maintaining high-speed operations. In contrast, the CY7C1460AV25 and CY7C1462AV25 provide slightly smaller capacities of 1 Megabit (128 K x 8) and 2 Megabits (256 K x 8) respectively, catering to varying system memory requirements.

All three devices utilize Cypress's advanced synchronous SRAM technology. This enables the chips to support burst read and write modes, allowing for rapid data transfer rates. The CY7C1464AV25 delivers a data access time of as low as 5.5 ns, making it highly efficient for data-intensive applications. Additionally, the standard operating voltage of 2.5V aids in reducing power consumption and improving overall system energy efficiency.

The chips are also characterized by a simple interface and compatibility with common bus protocols, which facilitates easy integration into existing systems. They feature a dual-port architecture, allowing multiple data transfers to occur simultaneously, significantly improving throughput.

With a commercial temperature range, all three devices offer reliability and are suited for a wide range of operating environments. The package options include a compact 44-pin TSOP, allowing for space-saving designs in modern electronics.

In summary, the Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 provide a powerful blend of capacity, speed, and efficiency, making them ideal choices for demanding applications in various sectors. Their advanced technologies and versatility make them excellent candidates for enhancing system performance while maintaining low power consumption and ensuring reliable operation in various conditions.
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