Cypress CY7C1462AV25, CY7C1464AV25 manual Switching Characteristics Over the Operating Range 21

Page 19

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Switching Characteristics Over the Operating Range [21, 22]

 

 

 

 

 

 

 

 

 

 

–250

–200

–167

 

Parameter

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

Unit

 

 

 

 

 

 

 

 

Min.

Max.

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

 

 

tPower[17]

 

VCC (typical) to the first access read or write

1

 

1

 

1

 

ms

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

 

Clock Cycle Time

4.0

 

5.0

 

6.0

 

ns

FMAX

 

Maximum Operating Frequency

 

250

 

200

 

167

MHz

tCH

 

Clock HIGH

1.5

 

2.0

 

2.4

 

ns

tCL

 

Clock LOW

1.5

 

2.0

 

2.4

 

ns

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCO

 

Data Output Valid After CLK Rise

 

2.6

 

3.2

 

3.4

ns

tEOV

 

 

 

LOW to Output Valid

 

2.6

 

3.0

 

3.4

ns

OE

 

 

 

tDOH

 

Data Output Hold After CLK Rise

1.0

 

1.5

 

1.5

 

ns

tCHZ

 

Clock to High-Z[18, 19, 20]

 

2.6

 

3.0

 

3.4

ns

tCLZ

 

Clock to Low-Z[18, 19, 20]

1.0

 

1.3

 

1.5

 

ns

tEOHZ

 

 

 

HIGH to Output High-Z[18, 19, 20]

 

2.6

 

3.0

 

3.4

ns

OE

 

 

 

tEOLZ

 

 

 

LOW to Output Low-Z[18, 19, 20]

0

 

0

 

0

 

ns

OE

 

 

 

Set-up Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

 

Address Set-up Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

tDS

 

Data Input Set-up Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

tCENS

 

 

 

 

 

 

Set-up Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

CEN

 

 

 

tWES

 

 

 

 

 

 

 

x Set-up Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

WE,

BW

 

 

 

tALS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADV/LD

Set-up Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

tCES

 

Chip Select Set-up

1.2

 

1.4

 

1.5

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAH

 

Address Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

tDH

 

Data Input Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

tCENH

 

 

 

 

Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

CEN

 

 

 

tWEH

 

 

 

 

 

 

 

x Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

WE,

BW

 

 

 

tALH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADV/LD

Hold after CLK Rise

0.3

 

0.4

 

0.5

 

ns

tCEH

 

Chip Select Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

Notes:

17.This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated.

18.tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

19.At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

20.This parameter is sampled and not 100% tested.

21.Timing reference is 1.25V when VDDQ = 2.5V and 0.9V when VDDQ = 1.8V.

22.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05354 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1460AV25 1M x Functional Description250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1462AV25 2M xLogic Block Diagram-CY7C1464AV25 512K x Selection Guide2M × Pin Configurations Pin Tqfp PinoutCY7C1462AV25 2M × ADV/LD Pin DefinitionsPin Name Type Pin Description Byte Write Select Inputs, active LOW. Qualified withClock input to the Jtag circuitry Power supply inputs to the core of the devicePower supply for the I/O circuitry Type Pin DescriptionBurst Write Accesses Single Read AccessesBurst Read Accesses Single Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Function CY7C1464AV25 Partial Write Cycle Description1, 2, 3Function CY7C1460AV25 BW d BW c BW b BW a Function CY7C1462AV25Performing a TAP Reset TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Test Access Port TAPTAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Description Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions 8V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeCY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball ID Ball Fbga Boundary Scan Order12Bit# Ball ID CY7C1464AV25 512K x Bit# Ball ID Ball Fbga Boundary Scan Order 12Ambient Range Electrical Characteristics Over the Operating Range14Maximum Ratings Operating RangeThermal Resistance Capacitance16AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 21Read/Write/Timing23, 24 Switching WaveformsNOP, Stall and Deselect Cycles23, 24 DON’T Care ZZ Mode Timing27Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm RXU ECN No Issue Date Orig. Description of ChangeDocument History SYT

CY7C1462AV25, CY7C1460AV25, CY7C1464AV25 specifications

The Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 are a family of high-performance synchronous SRAM devices that have been designed for applications requiring fast memory access and low latency. These memory chips are particularly appealing for systems in telecommunications, networking, and embedded applications due to their versatility and robust performance specifications.

One of the standout features of the CY7C1464AV25 series is their large capacities. The CY7C1464AV25 offers a capacity of 4 Megabits (512 K x 8), making it well-suited for applications that demand ample memory while maintaining high-speed operations. In contrast, the CY7C1460AV25 and CY7C1462AV25 provide slightly smaller capacities of 1 Megabit (128 K x 8) and 2 Megabits (256 K x 8) respectively, catering to varying system memory requirements.

All three devices utilize Cypress's advanced synchronous SRAM technology. This enables the chips to support burst read and write modes, allowing for rapid data transfer rates. The CY7C1464AV25 delivers a data access time of as low as 5.5 ns, making it highly efficient for data-intensive applications. Additionally, the standard operating voltage of 2.5V aids in reducing power consumption and improving overall system energy efficiency.

The chips are also characterized by a simple interface and compatibility with common bus protocols, which facilitates easy integration into existing systems. They feature a dual-port architecture, allowing multiple data transfers to occur simultaneously, significantly improving throughput.

With a commercial temperature range, all three devices offer reliability and are suited for a wide range of operating environments. The package options include a compact 44-pin TSOP, allowing for space-saving designs in modern electronics.

In summary, the Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 provide a powerful blend of capacity, speed, and efficiency, making them ideal choices for demanding applications in various sectors. Their advanced technologies and versatility make them excellent candidates for enhancing system performance while maintaining low power consumption and ensuring reliable operation in various conditions.
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