Cypress CY7C1460AV25 manual Scan Register Sizes, Identification Codes, Register Name Bit Size

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									CY7C1460AV25
									CY7C1462AV25
Scan Register Sizes									CY7C1464AV25
									CY7C1464AV25




Register Name							Bit Size (x36)	Bit Size (x18)		Bit Size (x72)

Instruction							3	3		3

Bypass							1	1		1

ID							32	32		32

Boundary Scan Order (165-ball FBGA package)							89	89		–

Boundary Scan Order (209-ball FBGA package)							–	–		138

Identification Codes

Instruction		Code						Description

EXTEST		000			Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
					Forces all SRAM outputs to High-Z state.
IDCODE		001			Loads the ID register with the vendor ID code and places the register between TDI and
					TDO. This operation does not affect SRAM operations.
SAMPLE Z		010			Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
					Forces all SRAM output drivers to a High-Z state.
RESERVED		011			Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD		100			Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
					Does not affect SRAM operation.
RESERVED		101			Do Not Use: This instruction is reserved for future use.

RESERVED		110			Do Not Use: This instruction is reserved for future use.

BYPASS		111			Places the bypass register between TDI and TDO. This operation does not affect SRAM
					operations.

Document #: 38-05354 Rev. *D

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1460AV25 1M x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1462AV25 2M xLogic Block Diagram-CY7C1464AV25 512K x 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV25 2M × Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsPin Name Type Pin Description ADV/LDType Pin Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Clock input to the Jtag circuitrySingle Write Accesses Single Read AccessesBurst Read Accesses Burst Write AccessesZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Function CY7C1462AV25 Partial Write Cycle Description1, 2, 3Function CY7C1460AV25 BW d BW c BW b BW a Function CY7C1464AV25Test Access Port TAP TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Performing a TAP Reset Bypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times8V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBit# Ball ID Ball Fbga Boundary Scan Order12CY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball ID Ball Fbga Boundary Scan Order 12 CY7C1464AV25 512K x Bit# Ball IDOperating Range Electrical Characteristics Over the Operating Range14Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance16Thermal Resistance Switching Characteristics Over the Operating Range 21 250 200 167 Parameter Description Unit Min MaxNOP, Stall and Deselect Cycles23, 24 Switching WaveformsRead/Write/Timing23, 24 ZZ Mode Timing27 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm SYT ECN No Issue Date Orig. Description of ChangeDocument History RXU