Cypress CY7C1462AV25 TAP Controller Block Diagram TAP Controller State Diagram, TAP Registers

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

IEEE 1149.1 Serial Boundary Scan (JTAG)

Test Data-In (TDI)

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 incor- porates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 2.5V/1.8V I/O logic level.

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alter- nately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most signif- icant bit (MSB) of any register. (See Tap Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

TAP Controller State Diagram

1

TEST-LOGIC

 

 

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

0

RUN-TEST/

1

SELECT

1

SELECT

1

IDLE

 

DR-SCAN

 

IR-SCAN

 

 

 

 

 

 

 

 

0

 

0

 

 

 

 

1

 

1

 

 

 

 

CAPTURE-DR

 

CAPTURE-IR

 

 

 

 

0

 

0

 

 

 

 

SHIFT-DR

0

SHIFT-IR

0

 

 

 

1

 

1

 

 

 

 

 

1

 

1

TDI

Selection Circuitry

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bypass Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

30

29

.

.

.

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Identification Register

 

 

 

 

 

 

 

 

 

 

x

.

.

.

.

.

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Boundary Scan Register

Selection Circuitry

TDO

EXIT1-DR

 

EXIT1-IR

 

 

0

 

 

0

 

PAUSE-DR

0

PAUSE-IR

0

 

1

 

 

1

 

0

 

 

0

 

 

EXIT2-DR

 

EXIT2-IR

 

 

1

 

 

1

 

UPDATE-DR

 

UPDATE-IR

 

1

0

 

1

0

 

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.

TCK

TMS

 

TAP CONTROLLER

 

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.

At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

Document #: 38-05354 Rev. *D

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1460AV25 1M x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1462AV25 2M xLogic Block Diagram-CY7C1464AV25 512K x 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV25 2M × Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsPin Name Type Pin Description ADV/LDType Pin Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Clock input to the Jtag circuitrySingle Write Accesses Single Read AccessesBurst Read Accesses Burst Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Function CY7C1462AV25 Partial Write Cycle Description1, 2, 3Function CY7C1460AV25 BW d BW c BW b BW a Function CY7C1464AV25Test Access Port TAP TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Performing a TAP ResetBypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times8V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionCY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball ID Ball Fbga Boundary Scan Order12Bit# Ball ID Ball Fbga Boundary Scan Order 12 CY7C1464AV25 512K x Bit# Ball IDOperating Range Electrical Characteristics Over the Operating Range14Maximum Ratings Ambient RangeThermal Resistance Capacitance16AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 21 250 200 167 Parameter Description Unit Min MaxRead/Write/Timing23, 24 Switching WaveformsNOP, Stall and Deselect Cycles23, 24 ZZ Mode Timing27 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm SYT ECN No Issue Date Orig. Description of ChangeDocument History RXU

CY7C1462AV25, CY7C1460AV25, CY7C1464AV25 specifications

The Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 are a family of high-performance synchronous SRAM devices that have been designed for applications requiring fast memory access and low latency. These memory chips are particularly appealing for systems in telecommunications, networking, and embedded applications due to their versatility and robust performance specifications.

One of the standout features of the CY7C1464AV25 series is their large capacities. The CY7C1464AV25 offers a capacity of 4 Megabits (512 K x 8), making it well-suited for applications that demand ample memory while maintaining high-speed operations. In contrast, the CY7C1460AV25 and CY7C1462AV25 provide slightly smaller capacities of 1 Megabit (128 K x 8) and 2 Megabits (256 K x 8) respectively, catering to varying system memory requirements.

All three devices utilize Cypress's advanced synchronous SRAM technology. This enables the chips to support burst read and write modes, allowing for rapid data transfer rates. The CY7C1464AV25 delivers a data access time of as low as 5.5 ns, making it highly efficient for data-intensive applications. Additionally, the standard operating voltage of 2.5V aids in reducing power consumption and improving overall system energy efficiency.

The chips are also characterized by a simple interface and compatibility with common bus protocols, which facilitates easy integration into existing systems. They feature a dual-port architecture, allowing multiple data transfers to occur simultaneously, significantly improving throughput.

With a commercial temperature range, all three devices offer reliability and are suited for a wide range of operating environments. The package options include a compact 44-pin TSOP, allowing for space-saving designs in modern electronics.

In summary, the Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 provide a powerful blend of capacity, speed, and efficiency, making them ideal choices for demanding applications in various sectors. Their advanced technologies and versatility make them excellent candidates for enhancing system performance while maintaining low power consumption and ensuring reliable operation in various conditions.
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