Cypress CY7C68013A manual Port E, T0OUT, T1OUT, T2OUT, RXD0OUT

Page 25

 

 

 

 

 

 

 

 

 

 

 

CY7C68013A, CY7C68014A

 

 

 

 

 

 

 

 

 

 

 

CY7C68015A, CY7C68016A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 11. FX2LP Pin Descriptions (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

128

 

100

56

56

56 VF-

Name

Type

Default

Description

 

 

TQFP

TQFP

SSOP

QFN

BGA

 

 

 

 

 

 

 

104

 

82

54

47

6B

PD2 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[10]

 

(PD2)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[10] is the bidirectional FIFO/GPIF data bus.

 

105

 

83

55

48

6A

PD3 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[11]

 

(PD3)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[11] is the bidirectional FIFO/GPIF data bus.

 

121

 

95

56

49

3B

PD4 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[12]

 

(PD4)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[12] is the bidirectional FIFO/GPIF data bus.

 

122

 

96

1

50

3A

PD5 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[13]

 

(PD5)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[13] is the bidirectional FIFO/GPIF data bus.

 

123

 

97

2

51

3C

PD6 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[14]

 

(PD6)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[14] is the bidirectional FIFO/GPIF data bus.

 

124

 

98

3

52

2A

PD7 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[15]

 

(PD7)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[15] is the bidirectional FIFO/GPIF data bus.

 

Port E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

108

 

86

 

 

 

 

 

PE0 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

T0OUT

 

(PE0)

PORTECFG.0 bit.

 

 

 

 

 

 

 

 

 

 

 

 

PE0 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

T0OUT is an active-HIGH signal from 8051

 

 

 

 

 

 

 

 

 

 

 

 

Timer-counter0. T0OUT outputs a high level for one

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT clock cycle when Timer0 overflows. If Timer0

 

 

 

 

 

 

 

 

 

 

 

 

is operated in Mode 3 (two separate timer/counters),

 

 

 

 

 

 

 

 

 

 

 

 

T0OUT is active when the low byte timer/counter

 

 

 

 

 

 

 

 

 

 

 

 

overflows.

 

109

 

87

 

 

 

 

 

PE1 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

T1OUT

 

(PE1)

PORTECFG.1 bit.

 

 

 

 

 

 

 

 

 

 

 

 

PE1 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

T1OUT is an active-HIGH signal from 8051

 

 

 

 

 

 

 

 

 

 

 

 

Timer-counter1. T1OUT outputs a high level for one

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT clock cycle when Timer1 overflows. If Timer1

 

 

 

 

 

 

 

 

 

 

 

 

is operated in Mode 3 (two separate timer/counters),

 

 

 

 

 

 

 

 

 

 

 

 

T1OUT is active when the low byte timer/counter

 

 

 

 

 

 

 

 

 

 

 

 

overflows.

 

110

 

88

 

 

 

 

 

PE2 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

T2OUT

 

(PE2)

PORTECFG.2 bit.

 

 

 

 

 

 

 

 

 

 

 

 

PE2 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

T2OUT is the active-HIGH output signal from 8051

 

 

 

 

 

 

 

 

 

 

 

 

Timer2. T2OUT is active (HIGH) for one clock cycle

 

 

 

 

 

 

 

 

 

 

 

 

when Timer/Counter 2 overflows.

 

111

 

89

 

 

 

 

 

PE3 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

RXD0OUT

 

(PE3)

PORTECFG.3 bit.

 

 

 

 

 

 

 

 

 

 

 

 

PE3 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

RXD0OUT is an active-HIGH signal from 8051 UART0.

 

 

 

 

 

 

 

 

 

 

 

 

If RXD0OUT is selected and UART0 is in Mode 0, this

 

 

 

 

 

 

 

 

 

 

 

 

pin provides the output data for UART0 only when it is

 

 

 

 

 

 

 

 

 

 

 

 

in sync mode. Otherwise it is a 1.

 

Document #: 38-08032 Rev. *L

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Contents Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16AFeatures CY7C68013A/14A only Logic Block DiagramFeatures CY7C68015A/16A only Functional Overview ApplicationsBus-powered Applications USB Boot MethodsReNumeration Interrupt SystemPriority INT2VEC Value Source INT2 USB InterruptsFIFO/GPIF Interrupt INT4 Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionInternal Code Memory, EA = Inside FX2LP Outside FX2LPExternal Code Memory, EA = Register AddressesEndpoint Configurations High -speed Mode Setup Data BufferEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytesMaster/Slave Control Signals 12.5 Default Full-Speed Alternate SettingsExternal Fifo Interface ArchitectureECC Generation7 Autopointer AccessGpif USB Uploads and DownloadsCompatible with Previous Generation EZ-USB FX2 18 I2C ControllerPart Number Conversion Table Package Description20 CY7C68013A/14A and CY7C68015A/16A Differences Pin AssignmentsIfclk PE0 PE1128 Pin Tqfp CY7C68013A/CY7C68014ACY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin SsopCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type DefaultFX2LP Pin Descriptions 56 VF Name Type Default DescriptionPort WU2 IFCONFIG1..0FIFOADR0 FIFOADR1PORTCCFG.0 GPIFADR0GPIFADR1 PORTCCFG.1T0OUT Port ET1OUT T2OUTINT6 RXD1OUTT2EX GPIFADR8Flagc FlagbCTL3 CTL4Ground FX2LP Register Summary Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Absolute Maximum Ratings Thermal CharacteristicsOperating Conditions ΘJc + θCaAC Electrical Characteristics DC CharacteristicsUSB Transceiver Clkout Program Memory ReadProgram Memory Read Parameters Description Min Typ Max Unit CLKOUT17 Data Memory ReadData Memory Read Parameters Description Min Typ Max Unit Stretch = Data Memory WriteData Memory Write Parameters Description Min Max Unit WR# Strobe Function when Portc is Accessed by Portc Strobe Feature TimingsGpif Synchronous Signals Timing Diagram20 Gpif Synchronous SignalsSlave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Synchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSingle and Burst Synchronous Read Example Sequence Diagram10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous WriteIdeal for non-battery powered applications Ideal for battery powered applicationsOrdering Information Development Tool KitLead Shrunk Small Outline Package O56 Package DiagramsLead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesIssue Orig. Description of Change Date Pyrs Cmcc

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.
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