Cypress manual CY7C68013A/CY7C68014A

Page 17

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A

Figure 8. CY7C68013A/CY7C68014A 100-pin TQFP Pin Assignment

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

PD7/FD15 GND CLKOUT

PD6/FD14

PD5/FD13

PD4/FD12

PE7/GPIFADR8 GND

PE6/T2EX

PE5/INT6

PE4/RXD1OUT

PE3/RXD0OUT

PE2/T2OUT

PE1/T1OUT

PE0/T0OUT

INT5# VCC

PD3/FD11

PD2/FD10

PD1/FD9

VCC

PD0/FD8

1

GND

*WAKEUP

2

RDY0/*SLRD

VCC

3

RDY1/*SLWR

RESET#

4

RDY2

CTL5

5

RDY3

GND

6

RDY4

PA7/*FLAGD/SLCS#

7

RDY5

PA6/*PKTEND

8

AVCC

PA5/FIFOADR1

9

XTALOUT

PA4/FIFOADR0

10

XTALIN

PA3/*WU2

11

AGND

PA2/*SLOE

12

NC

PA1/INT1#

13

NC

PA0/INT0#

14

CY7C68013A/CY7C68014A

NC

VCC

15

AVCC

100-pin TQFP

GND

16

DPLUS

PC7/GPIFADR7

17

DMINUS

PC6/GPIFADR6

18

AGND

PC5/GPIFADR5

19

VCC

PC4/GPIFADR4

20

GND

PC3/GPIFADR3

21

INT4

PC2/GPIFADR2

22

T0

PC1/GPIFADR1

23

T1

PC0/GPIFADR0

24

25

T2

CTL2/*FLAGC

*IFCLK

CTL1/*FLAGB

26

RESERVED

CTL0/*FLAGA

27

BKPT

VCC

28

SCL

CTL4

29

SDA

CTL3

30

	RD#		WR#		VCC		PB0/FD0		PB1/FD1		PB2/FD2		PB3/FD3		VCC		GND		TXD0		RXD0		TXD1		RXD1		PB4/FD4		PB5/FD5		PB6/FD6		PB7/FD7		GND		VCC		GND

	31		32		33		34		35		36		37		38		39		40		41		42		43		44		45		46		47		48		49		50

* denotes programmable polarity

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Document #: 38-08032 Rev. *L

Page 17 of 62

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Contents Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16AFeatures CY7C68015A/16A only Logic Block DiagramFeatures CY7C68013A/14A only Functional Overview ApplicationsBus-powered Applications USB Boot MethodsReNumeration Interrupt SystemFIFO/GPIF Interrupt INT4 INT2 USB InterruptsPriority INT2VEC Value Source Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionInternal Code Memory, EA = Inside FX2LP Outside FX2LPExternal Code Memory, EA = Register AddressesEndpoint Configurations High -speed Mode Setup Data BufferEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytesMaster/Slave Control Signals 12.5 Default Full-Speed Alternate SettingsExternal Fifo Interface ArchitectureECC Generation7 Autopointer AccessGpif USB Uploads and DownloadsCompatible with Previous Generation EZ-USB FX2 18 I2C ControllerPart Number Conversion Table Package Description20 CY7C68013A/14A and CY7C68015A/16A Differences Pin AssignmentsIfclk PE0 PE1128 Pin Tqfp CY7C68013A/CY7C68014ACY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin SsopCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type DefaultPort 56 VF Name Type Default DescriptionFX2LP Pin Descriptions WU2 IFCONFIG1..0FIFOADR0 FIFOADR1PORTCCFG.0 GPIFADR0GPIFADR1 PORTCCFG.1T0OUT Port ET1OUT T2OUTINT6 RXD1OUTT2EX GPIFADR8Flagc FlagbCTL3 CTL4Ground FX2LP Register Summary Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Absolute Maximum Ratings Thermal CharacteristicsOperating Conditions ΘJc + θCaUSB Transceiver DC CharacteristicsAC Electrical Characteristics Program Memory Read Parameters Description Min Typ Max Unit Program Memory ReadClkout Data Memory Read Parameters Description Min Typ Max Unit Data Memory ReadCLKOUT17 Data Memory Write Parameters Description Min Max Unit Data Memory WriteStretch = WR# Strobe Function when Portc is Accessed by Portc Strobe Feature TimingsGpif Synchronous Signals Timing Diagram20 Gpif Synchronous SignalsSlave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Synchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSingle and Burst Synchronous Read Example Sequence Diagram10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous WriteIdeal for non-battery powered applications Ideal for battery powered applicationsOrdering Information Development Tool KitLead Shrunk Small Outline Package O56 Package DiagramsLead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesIssue Orig. Description of Change Date Pyrs Cmcc

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.