Cypress CY7C68013A INT2 USB Interrupts, Priority INT2VEC Value Source, FIFO/GPIF Interrupt INT4

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CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

The FX2LP jump instruction is encoded as follows:

Table 3. INT2 USB Interrupts

USB INTERRUPT TABLE FOR INT2

Priority

INT2VEC Value

Source

Notes

1

00

SUDAV

Setup Data Available

 

 

 

 

2

04

SOF

Start of Frame (or microframe)

 

 

 

 

3

08

SUTOK

Setup Token Received

 

 

 

 

4

0C

SUSPEND

USB Suspend request

 

 

 

 

5

10

USB RESET

Bus reset

 

 

 

 

6

14

HISPEED

Entered high-speed operation

 

 

 

 

7

18

EP0ACK

FX2LP ACK’d the CONTROL Handshake

 

 

 

 

8

1C

 

reserved

 

 

 

 

9

20

EP0-IN

EP0-IN ready to be loaded with data

 

 

 

 

10

24

EP0-OUT

EP0-OUT has USB data

 

 

 

 

11

28

EP1-IN

EP1-IN ready to be loaded with data

 

 

 

 

12

2C

EP1-OUT

EP1-OUT has USB data

 

 

 

 

13

30

EP2

IN: buffer available. OUT: buffer has data

 

 

 

 

14

34

EP4

IN: buffer available. OUT: buffer has data

 

 

 

 

15

38

EP6

IN: buffer available. OUT: buffer has data

 

 

 

 

16

3C

EP8

IN: buffer available. OUT: buffer has data

 

 

 

 

17

40

IBN

IN-Bulk-NAK (any IN endpoint)

 

 

 

 

18

44

 

reserved

 

 

 

 

19

48

EP0PING

EP0 OUT was Pinged and it NAK’d

 

 

 

 

20

4C

EP1PING

EP1 OUT was Pinged and it NAK’d

 

 

 

 

21

50

EP2PING

EP2 OUT was Pinged and it NAK’d

 

 

 

 

22

54

EP4PING

EP4 OUT was Pinged and it NAK’d

 

 

 

 

23

58

EP6PING

EP6 OUT was Pinged and it NAK’d

 

 

 

 

24

5C

EP8PING

EP8 OUT was Pinged and it NAK’d

 

 

 

 

25

60

ERRLIMIT

Bus errors exceeded the programmed limit

 

 

 

 

26

64

 

 

 

 

 

 

27

68

 

reserved

 

 

 

 

28

6C

 

reserved

 

 

 

 

29

70

EP2ISOERR

ISO EP2 OUT PID sequence error

 

 

 

 

30

74

EP4ISOERR

ISO EP4 OUT PID sequence error

 

 

 

 

31

78

EP6ISOERR

ISO EP6 OUT PID sequence error

 

 

 

 

32

7C

EP8ISOERR

ISO EP8 OUT PID sequence error

 

 

 

 

If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs the jump to the correct address out of the 27 addresses within the page.

3.8.3 FIFO/GPIF Interrupt (INT4)

Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.

Document #: 38-08032 Rev. *L

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Contents Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16AFeatures CY7C68015A/16A only Logic Block DiagramFeatures CY7C68013A/14A only Functional Overview ApplicationsBus-powered Applications USB Boot MethodsReNumeration Interrupt SystemFIFO/GPIF Interrupt INT4 INT2 USB InterruptsPriority INT2VEC Value Source Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionInternal Code Memory, EA = Inside FX2LP Outside FX2LPExternal Code Memory, EA = Register AddressesEndpoint Configurations High -speed Mode Setup Data BufferEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytesMaster/Slave Control Signals 12.5 Default Full-Speed Alternate SettingsExternal Fifo Interface ArchitectureECC Generation7 Autopointer AccessGpif USB Uploads and DownloadsCompatible with Previous Generation EZ-USB FX2 18 I2C ControllerPart Number Conversion Table Package Description20 CY7C68013A/14A and CY7C68015A/16A Differences Pin AssignmentsIfclk PE0 PE1128 Pin Tqfp CY7C68013A/CY7C68014ACY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin SsopCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type DefaultPort 56 VF Name Type Default DescriptionFX2LP Pin Descriptions WU2 IFCONFIG1..0FIFOADR0 FIFOADR1PORTCCFG.0 GPIFADR0GPIFADR1 PORTCCFG.1T0OUT Port ET1OUT T2OUTINT6 RXD1OUTT2EX GPIFADR8Flagc FlagbCTL3 CTL4Ground FX2LP Register Summary Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Absolute Maximum Ratings Thermal CharacteristicsOperating Conditions ΘJc + θCaUSB Transceiver DC CharacteristicsAC Electrical Characteristics Program Memory Read Parameters Description Min Typ Max Unit Program Memory ReadClkout Data Memory Read Parameters Description Min Typ Max Unit Data Memory ReadCLKOUT17 Data Memory Write Parameters Description Min Max Unit Data Memory WriteStretch = WR# Strobe Function when Portc is Accessed by Portc Strobe Feature TimingsGpif Synchronous Signals Timing Diagram20 Gpif Synchronous SignalsSlave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Synchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSingle and Burst Synchronous Read Example Sequence Diagram10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous WriteIdeal for non-battery powered applications Ideal for battery powered applicationsOrdering Information Development Tool KitLead Shrunk Small Outline Package O56 Package DiagramsLead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesIssue Orig. Description of Change Date Pyrs Cmcc

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.
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