Cypress manual CY7C68013A/CY7C68014A, Pin Tqfp

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CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A

Figure 7. CY7C68013A/CY7C68014A 128-pin TQFP Pin Assignment

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

GND

A10

A9

A8

PD7/FD15 GND

PD6/FD14

PD5/FD13

PD4/FD12

A7

A6

A5

A4

GND

PE7/GPIFADR8

PE6/T2EX

PE5/INT6

PE4/RXD1OUT

PE3/RXD0OUT

PE2/T2OUT

PE1/T1OUT

PE0/T0OUT

VCC

INT5#

PD3/FD11

PD2/FD10

PD1/FD9

VCC

1

CLKOUT

PD0/FD8

2

VCC

*WAKEUP

3

RDY0/*SLRD

RESET#

4

RDY1/*SLWR

CTL5

5

RDY2

A3

6

RDY3

A2

7

RDY4

A1

8

RDY5

A0

9

AVCC

GND

10

XTALOUT

11

PA7/*FLAGD/SLCS#

12

XTALIN

PA6/*PKTEND

AGND

13

PA5/FIFOADR1

NC

14

PA4/FIFOADR0

NC

D7

15

NC

D6

16

AVCC

D5

17

DPLUS

CY7C68013A/CY7C68014A

PA3/*WU2

18

DMINUS

128-pin TQFP

PA2/*SLOE

19

AGND

20

PA1/INT1#

21

A11

PA0/INT0#

22

A12

VCC

A13

GND

23

A14

24

PC7/GPIFADR7

25

A15

PC6/GPIFADR6

VCC

26

PC5/GPIFADR5

GND

27

PC4/GPIFADR4

INT4

28

PC3/GPIFADR3

29

T0

PC2/GPIFADR2

30

T1

PC1/GPIFADR1

31

T2

PC0/GPIFADR0

32

*IFCLK

CTL2/*FLAGC

RESERVED

CTL1/*FLAGB

33

BKPT

34

CTL0/*FLAGA

35

EA

VCC

SCL

CTL4

36

SDA

CTL3

37

OE#

GND

38

PB0/FD0 VCC CS# WR# RD# PSEN#

PB1/FD1

PB2/FD2

PB3/FD3

PB4/FD4

PB5/FD5

PB6/FD6

PB7/FD7

TXD0 GND VCC

RXD0

TXD1

RXD1

D0 GND

VCC D4 D3 D2 D1

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

* denotes programmable polarity

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

Document #: 38-08032 Rev. *L

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Contents Features CY7C68013A/14A/15A/16A Cypress Semiconductor Corporation 198 Champion CourtFeatures CY7C68013A/14A only Logic Block DiagramFeatures CY7C68015A/16A only Applications Functional OverviewUSB Boot Methods Bus-powered ApplicationsReNumeration Interrupt SystemPriority INT2VEC Value Source INT2 USB InterruptsFIFO/GPIF Interrupt INT4 Reset and Wakeup Reset PinReset Timing Values Condition Program/Data RAMInside FX2LP Outside FX2LP Internal Code Memory, EA =Register Addresses External Code Memory, EA =Setup Data Buffer Endpoint Configurations High -speed ModeEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytes12.5 Default Full-Speed Alternate Settings Master/Slave Control SignalsExternal Fifo Interface ArchitectureAutopointer Access ECC Generation7Gpif USB Uploads and Downloads18 I2C Controller Compatible with Previous Generation EZ-USB FX2Part Number Conversion Table Package DescriptionPin Assignments 20 CY7C68013A/14A and CY7C68015A/16A DifferencesIfclk PE0 PE1128 CY7C68013A/CY7C68014A Pin TqfpCY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop CY7C68013A/CY7C68014A 56-pin Ssop Pin AssignmentCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View FX2LP Pin Descriptions 128 100 56 VF Name Type Default CY7C68013A/15A Pin DescriptionsFX2LP Pin Descriptions 56 VF Name Type Default DescriptionPort IFCONFIG1..0 WU2FIFOADR0 FIFOADR1GPIFADR0 PORTCCFG.0GPIFADR1 PORTCCFG.1Port E T0OUTT1OUT T2OUTRXD1OUT INT6T2EX GPIFADR8Flagb FlagcCTL3 CTL4Ground Register Summary FX2LP Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Thermal Characteristics Absolute Maximum RatingsOperating Conditions ΘJc + θCaAC Electrical Characteristics DC CharacteristicsUSB Transceiver Clkout Program Memory ReadProgram Memory Read Parameters Description Min Typ Max Unit CLKOUT17 Data Memory ReadData Memory Read Parameters Description Min Typ Max Unit Stretch = Data Memory WriteData Memory Write Parameters Description Min Max Unit Portc Strobe Feature Timings WR# Strobe Function when Portc is Accessed byGpif Synchronous Signals Gpif Synchronous Signals Timing Diagram20Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataFIFOADR10 to SLRD/SLWR/PKTEND Setup Time Slave Fifo Synchronous AddressSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSequence Diagram Single and Burst Synchronous Read Example10.17.2 Single and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Read Sequence and Timing Diagram20Sequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram20Ideal for battery powered applications Ideal for non-battery powered applicationsOrdering Information Development Tool KitPackage Diagrams Lead Shrunk Small Outline Package O56Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 PCB Layout Recommendations Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56Quad Flat Package No Leads QFN Package Design Notes Cross-section of the Area Underneath the QFN PackageIssue Orig. Description of Change Date Cmcc Pyrs

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.