Cypress CY7C68013A manual Issue Orig. Description of Change Date

Page 61

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Document History Page

Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller

Document Number: 38-08032

REV.

ECN NO.

Issue

Orig. of

Description of Change

Date

Change

 

 

 

 

 

 

 

 

**

124316

03/17/03

VCS

New data sheet

 

 

 

 

 

*A

128461

09/02/03

VCS

Added PN CY7C68015A throughout data sheet

 

 

 

 

Modified Figure 1 to add ECC block and fix errors

 

 

 

 

Removed word “compatible” where associated with I2C

 

 

 

 

Corrected grammar and formatting in various locations

 

 

 

 

Updated Sections 3.2.1, 3.9, 3.11, Table 9, Section 5.0

 

 

 

 

Added Sections 3.15, 3.18.4, 3.20

 

 

 

 

Modified Figure 5 for clarity

 

 

 

 

Updated Figure 36 to match current spec revision

*B

130335

10/09/03

KKV

Restored PRELIMINARY to header (had been removed in error from rev. *A)

 

 

 

 

 

*C

131673

02/12/04

KKU

Section 8.1 changed “certified” to “compliant”

 

 

 

 

Table 14 added parameter VIH_X and VIL_X

 

 

 

 

Added Sequence diagrams Section 9.16

 

 

 

 

Updated Ordering information with lead-free parts

 

 

 

 

Updated Registry Summary

 

 

 

 

Section 3.12.4:example changed to column 8 from column 9

 

 

 

 

Updated Figure 14 memory write timing Diagram

 

 

 

 

Updated section 3.9 (reset)

 

 

 

 

Updated section 3.15 ECC Generation

*D

230713

See ECN

KKU

Changed Lead free Marketing part numbers in Table 33 as per spec change in 28-00054.

 

 

 

 

 

*E

242398

See ECN

TMD

Minor Change: data sheet posted to the web,

 

 

 

 

 

*F

271169

See ECN

MON

Added USB-IF Test ID number

 

 

 

 

Added USB 2.0 logo

 

 

 

 

Added values for Isusp, Icc, Power Dissipation, Vih_x, Vil_x

 

 

 

 

Changed VCC from + 10% to + 5%

 

 

 

 

Changed E-Pad size to 4.3 mm x 5.0 mm

 

 

 

 

Changed PKTEND to FLAGS output propagation delay (asynchronous interface) in

 

 

 

 

Table 28 from a max value of 70 ns to 115 ns

*G

316313

See ECN

MON

Removed CY7C68013A-56PVXCT part availability

 

 

 

 

Added parts ideal for battery powered applications: CY7C68014A, CY7C68016A

 

 

 

 

Provided additional timing restrictions and requirement about the use of PKETEND pin to

 

 

 

 

commit a short one byte/word packet subsequent to committing a packet automatically

 

 

 

 

(when in auto mode).

 

 

 

 

Added Min Vcc Ramp Up time (0 to 3.3v)

*H

338901

See ECN

MON

Added information about the AUTOPTR1/AUTOPTR2 address timing with regards to data

 

 

 

 

memory read/write timing diagram.

 

 

 

 

Removed TBD for Min value of Clock to FIFO Data Output Propagation Delay (tXFD) for

 

 

 

 

Slave FIFO Synchronous Read

 

 

 

 

Changed Table 33 to include part CY7C68016A-56LFXC in the part listed for battery

 

 

 

 

powered applications

 

 

 

 

Added register GPCR2 in register summary

*I

371097

See ECN

MON

Added timing for strobing RD#/WR# signals when using PortC strobe feature (Section 10.5)

 

 

 

 

 

*J

397239

See ECN

MON

Removed XTALINSRC register from register summary.

 

 

 

 

Changed Vcc margins to +10%

 

 

 

 

Added 56-pin VFBGA Pin Package Diagram

 

 

 

 

Added 56-pin VFBGA definition in pin listing

 

 

 

 

Added RDK part number to the Ordering Information table

Document #: 38-08032 Rev. *L

Page 61 of 62

[+] Feedback

Page 60 Page 62
Image 61
Page 60 Page 62
Contents Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16AFeatures CY7C68013A/14A only Logic Block DiagramFeatures CY7C68015A/16A only Functional Overview ApplicationsBus-powered Applications USB Boot MethodsReNumeration Interrupt SystemPriority INT2VEC Value Source INT2 USB InterruptsFIFO/GPIF Interrupt INT4 Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionInternal Code Memory, EA = Inside FX2LP Outside FX2LPExternal Code Memory, EA = Register AddressesEndpoint Configurations High -speed Mode Setup Data BufferEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytesMaster/Slave Control Signals 12.5 Default Full-Speed Alternate SettingsExternal Fifo Interface ArchitectureECC Generation7 Autopointer AccessGpif USB Uploads and DownloadsCompatible with Previous Generation EZ-USB FX2 18 I2C ControllerPart Number Conversion Table Package Description20 CY7C68013A/14A and CY7C68015A/16A Differences Pin AssignmentsIfclk PE0 PE1128 Pin Tqfp CY7C68013A/CY7C68014ACY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin SsopCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type DefaultFX2LP Pin Descriptions 56 VF Name Type Default DescriptionPort WU2 IFCONFIG1..0FIFOADR0 FIFOADR1PORTCCFG.0 GPIFADR0GPIFADR1 PORTCCFG.1T0OUT Port ET1OUT T2OUTINT6 RXD1OUTT2EX GPIFADR8Flagc FlagbCTL3 CTL4Ground FX2LP Register Summary Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Absolute Maximum Ratings Thermal CharacteristicsOperating Conditions ΘJc + θCaAC Electrical Characteristics DC CharacteristicsUSB Transceiver Clkout Program Memory ReadProgram Memory Read Parameters Description Min Typ Max Unit CLKOUT17 Data Memory ReadData Memory Read Parameters Description Min Typ Max Unit Stretch = Data Memory WriteData Memory Write Parameters Description Min Max Unit WR# Strobe Function when Portc is Accessed by Portc Strobe Feature TimingsGpif Synchronous Signals Timing Diagram20 Gpif Synchronous SignalsSlave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Synchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSingle and Burst Synchronous Read Example Sequence Diagram10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous WriteIdeal for non-battery powered applications Ideal for battery powered applicationsOrdering Information Development Tool KitLead Shrunk Small Outline Package O56 Package DiagramsLead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesIssue Orig. Description of Change Date Pyrs Cmcc

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.
Top Page Image Contents