Cypress manual CY7C68013A/15A Pin Descriptions

Page 21

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

4.1CY7C68013A/15A Pin Descriptions

The FX2LP Pin Descriptions follows.[10]

Table 11. FX2LP Pin Descriptions

128

100

56

56

56 VF-

Name

Type

Default

Description

TQFP

TQFP

SSOP

QFN

BGA

 

 

 

 

10

9

10

3

2D

AVCC

Power

N/A

Analog VCC. Connect this pin to 3.3V power source.

 

 

 

 

 

 

 

 

This signal provides power to the analog section of the

 

 

 

 

 

 

 

 

chip.

17

16

14

7

1D

AVCC

Power

N/A

Analog VCC. Connect this pin to 3.3V power source.

 

 

 

 

 

 

 

 

This signal provides power to the analog section of the

 

 

 

 

 

 

 

 

chip.

13

12

13

6

2F

AGND

Ground

N/A

Analog Ground. Connect to ground with as short a path

 

 

 

 

 

 

 

 

as possible.

20

19

17

10

1F

AGND

Ground

N/A

Analog Ground. Connect to ground with as short a path

 

 

 

 

 

 

 

 

as possible.

19

18

16

9

1E

DMINUS

IO/Z

Z

USB D– Signal. Connect to the USB D– signal.

18

17

15

8

2E

DPLUS

IO/Z

Z

USB D+ Signal. Connect to the USB D+ signal.

 

 

 

 

 

 

 

 

 

94

 

 

 

 

A0

Output

L

8051 Address Bus. This bus is driven at all times.

 

 

 

 

 

 

 

 

When the 8051 is addressing internal RAM it reflects

95

 

 

 

 

A1

Output

L

 

 

 

 

the internal address.

 

 

 

 

 

 

 

 

96

 

 

 

 

A2

Output

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

97

 

 

 

 

A3

Output

L

 

 

 

 

 

 

 

 

 

 

117

 

 

 

 

A4

Output

L

 

 

 

 

 

 

 

 

 

 

118

 

 

 

 

A5

Output

L

 

 

 

 

 

 

 

 

 

 

119

 

 

 

 

A6

Output

L

 

 

 

 

 

 

 

 

 

 

120

 

 

 

 

A7

Output

L

 

 

 

 

 

 

 

 

 

 

126

 

 

 

 

A8

Output

L

 

 

 

 

 

 

 

 

 

 

127

 

 

 

 

A9

Output

L

 

 

 

 

 

 

 

 

 

 

128

 

 

 

 

A10

Output

L

 

 

 

 

 

 

 

 

 

 

21

 

 

 

 

A11

Output

L

 

 

 

 

 

 

 

 

 

 

22

 

 

 

 

A12

Output

L

 

 

 

 

 

 

 

 

 

 

23

 

 

 

 

A13

Output

L

 

 

 

 

 

 

 

 

 

 

24

 

 

 

 

A14

Output

L

 

 

 

 

 

 

 

 

 

 

25

 

 

 

 

A15

Output

L

 

 

 

 

 

 

 

 

 

 

59

 

 

 

 

D0

IO/Z

Z

8051 Data Bus. This bidirectional bus is high

 

 

 

 

 

 

 

 

impedance when inactive, input for bus reads, and

60

 

 

 

 

D1

IO/Z

Z

 

 

 

 

output for bus writes. The data bus is used for external

 

 

 

 

 

 

 

 

61

 

 

 

 

D2

IO/Z

Z

 

 

 

 

8051 program and data memory. The data bus is active

62

 

 

 

 

D3

IO/Z

Z

only for external bus accesses, and is driven LOW in

 

 

 

 

 

 

 

 

suspend.

63

 

 

 

 

D4

IO/Z

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

86

 

 

 

 

D5

IO/Z

Z

 

 

 

 

 

 

 

 

 

 

87

 

 

 

 

D6

IO/Z

Z

 

 

 

 

 

 

 

 

 

 

88

 

 

 

 

D7

IO/Z

Z

 

 

 

 

 

 

 

 

 

 

39

 

 

 

 

PSEN#

Output

H

Program Store Enable. This active-LOW signal

 

 

 

 

 

 

 

 

indicates an 8051 code fetch from external memory. It

 

 

 

 

 

 

 

 

is active for program memory fetches from

 

 

 

 

 

 

 

 

0x4000–0xFFFF when the EA pin is LOW, or from

 

 

 

 

 

 

 

 

0x0000–0xFFFF when the EA pin is HIGH.

Note

 

 

 

 

 

 

 

 

10.Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in standby. Note also that no pins should be driven while the device is powered down.

Document #: 38-08032 Rev. *L

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Contents Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16ALogic Block Diagram Features CY7C68013A/14A onlyFeatures CY7C68015A/16A only Functional Overview ApplicationsBus-powered Applications USB Boot MethodsReNumeration Interrupt SystemINT2 USB Interrupts Priority INT2VEC Value SourceFIFO/GPIF Interrupt INT4 Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionInternal Code Memory, EA = Inside FX2LP Outside FX2LPExternal Code Memory, EA = Register AddressesEndpoint Configurations High -speed Mode Setup Data BufferEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytesMaster/Slave Control Signals 12.5 Default Full-Speed Alternate SettingsExternal Fifo Interface ArchitectureECC Generation7 Autopointer AccessGpif USB Uploads and DownloadsCompatible with Previous Generation EZ-USB FX2 18 I2C ControllerPart Number Conversion Table Package Description20 CY7C68013A/14A and CY7C68015A/16A Differences Pin AssignmentsIfclk PE0 PE1128 Pin Tqfp CY7C68013A/CY7C68014ACY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin SsopCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type Default56 VF Name Type Default Description FX2LP Pin DescriptionsPort WU2 IFCONFIG1..0FIFOADR0 FIFOADR1PORTCCFG.0 GPIFADR0GPIFADR1 PORTCCFG.1T0OUT Port ET1OUT T2OUTINT6 RXD1OUTT2EX GPIFADR8Flagc FlagbCTL3 CTL4Ground FX2LP Register Summary Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Absolute Maximum Ratings Thermal CharacteristicsOperating Conditions ΘJc + θCaDC Characteristics AC Electrical CharacteristicsUSB Transceiver Program Memory Read ClkoutProgram Memory Read Parameters Description Min Typ Max Unit Data Memory Read CLKOUT17Data Memory Read Parameters Description Min Typ Max Unit Data Memory Write Stretch =Data Memory Write Parameters Description Min Max Unit WR# Strobe Function when Portc is Accessed by Portc Strobe Feature TimingsGpif Synchronous Signals Timing Diagram20 Gpif Synchronous SignalsSlave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Synchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSingle and Burst Synchronous Read Example Sequence Diagram10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous WriteIdeal for non-battery powered applications Ideal for battery powered applicationsOrdering Information Development Tool KitLead Shrunk Small Outline Package O56 Package DiagramsLead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesIssue Orig. Description of Change Date Pyrs Cmcc

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.
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