Cypress CY7C68013A manual Slave Fifo Asynchronous Write, Slave Fifo Synchronous Packet End Strobe

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CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

10.10 Slave FIFO Asynchronous Write

Figure 21. Slave FIFO Asynchronous Write Timing Diagram[20]

tWRpwh

SLWR

tWRpwl

 

 

 

 

tSFD

tFDH

DATA

 

 

FLAGS

tXFD

 

Table 25. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [23]

Parameter

Description

Min

Max

Unit

tWRpwl

SLWR Pulse LOW

50

 

ns

tWRpwh

SLWR Pulse HIGH

70

 

ns

tSFD

SLWR to FIFO DATA Setup Time

10

 

ns

tFDH

FIFO DATA to SLWR Hold Time

10

 

ns

tXFD

SLWR to FLAGS Output Propagation Delay

 

70

ns

10.11 Slave FIFO Synchronous Packet End Strobe

Figure 22. Slave FIFO Synchronous Packet End Strobe Timing Diagram[20]

IFCLK

PKTEND

FLAGS

tPEH

tSPE

tXFLG

Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK[21]

Parameter

Description

Min

Max

Unit

tIFCLK

IFCLK Period

20.83

 

ns

tSPE

PKTEND to Clock Setup Time

14.6

 

ns

tPEH

Clock to PKTEND Hold Time

0

 

ns

tXFLG

Clock to FLAGS Output Propagation Delay

 

9.5

ns

Table 27. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK[21]

 

Parameter

Description

Min

Max

Unit

tIFCLK

IFCLK Period

20.83

200

ns

tSPE

PKTEND to Clock Setup Time

8.6

 

ns

tPEH

Clock to PKTEND Hold Time

2.5

 

ns

tXFLG

Clock to FLAGS Output Propagation Delay

 

13.5

ns

Document #: 38-08032 Rev. *L

 

 

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Contents Features CY7C68013A/14A/15A/16A Cypress Semiconductor Corporation 198 Champion CourtFeatures CY7C68013A/14A only Logic Block DiagramFeatures CY7C68015A/16A only Applications Functional OverviewReNumeration USB Boot MethodsBus-powered Applications Interrupt SystemPriority INT2VEC Value Source INT2 USB InterruptsFIFO/GPIF Interrupt INT4 Reset and Wakeup Reset PinReset Timing Values Condition Program/Data RAMInside FX2LP Outside FX2LP Internal Code Memory, EA =Register Addresses External Code Memory, EA =Endpoint RAM Setup Data BufferEndpoint Configurations High -speed Mode Size × 64 bytes Endpoints 0 × 512 bytesExternal Fifo Interface 12.5 Default Full-Speed Alternate SettingsMaster/Slave Control Signals ArchitectureGpif Autopointer AccessECC Generation7 USB Uploads and DownloadsPart Number Conversion Table 18 I2C ControllerCompatible with Previous Generation EZ-USB FX2 Package DescriptionIfclk PE0 Pin Assignments20 CY7C68013A/14A and CY7C68015A/16A Differences PE1128 CY7C68013A/CY7C68014A Pin TqfpCY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop CY7C68013A/CY7C68014A 56-pin Ssop Pin AssignmentCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View FX2LP Pin Descriptions 128 100 56 VF Name Type Default CY7C68013A/15A Pin DescriptionsFX2LP Pin Descriptions 56 VF Name Type Default DescriptionPort FIFOADR0 IFCONFIG1..0WU2 FIFOADR1GPIFADR1 GPIFADR0PORTCCFG.0 PORTCCFG.1T1OUT Port ET0OUT T2OUTT2EX RXD1OUTINT6 GPIFADR8CTL3 FlagbFlagc CTL4Ground Register Summary FX2LP Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Operating Conditions Thermal CharacteristicsAbsolute Maximum Ratings ΘJc + θCaAC Electrical Characteristics DC CharacteristicsUSB Transceiver Clkout Program Memory ReadProgram Memory Read Parameters Description Min Typ Max Unit CLKOUT17 Data Memory ReadData Memory Read Parameters Description Min Typ Max Unit Stretch = Data Memory WriteData Memory Write Parameters Description Min Max Unit Portc Strobe Feature Timings WR# Strobe Function when Portc is Accessed byGpif Synchronous Signals Gpif Synchronous Signals Timing Diagram20Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Asynchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Synchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSequence Diagram Single and Burst Synchronous Read Example10.17.2 Single and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Read Sequence and Timing Diagram20Sequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram20Ordering Information Ideal for battery powered applicationsIdeal for non-battery powered applications Development Tool KitPackage Diagrams Lead Shrunk Small Outline Package O56Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 PCB Layout Recommendations Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56Quad Flat Package No Leads QFN Package Design Notes Cross-section of the Area Underneath the QFN PackageIssue Orig. Description of Change Date Cmcc Pyrs

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.