Cypress CY7C68013A manual FX2LP Register Summary

Page 29

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

5. Register Summary

FX2LP register bit definitions are described in the FX2LP TRM in greater detail.

Table 12. FX2LP Register Summary

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

 

 

GPIF Waveform Memories

 

 

 

 

 

 

 

 

 

 

 

E400

128

WAVEDATA

GPIF Waveform

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

Descriptor 0, 1, 2, 3 data

 

 

 

 

 

 

 

 

 

 

E480

128

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GENERAL CONFIGURATION

 

 

 

 

 

 

 

 

 

 

 

E50D

 

GPCR2

General Purpose Configu-

reserved

reserved

reserved

FULL_SPEE

reserved

reserved

reserved

reserved

00000000

R

 

 

 

ration Register 2

 

 

 

D_ONLY

 

 

 

 

 

 

E600

1

CPUCS

CPU Control & Status

0

0

PORTCSTB

CLKSPD1

CLKSPD0

CLKINV

CLKOE

8051RES

00000010

rrbbbbbr

E601

1

IFCONFIG

Interface Configuration

IFCLKSRC

3048MHZ

IFCLKOE

IFCLKPOL

ASYNC

GSTATE

IFCFG1

IFCFG0

10000000

RW

 

 

 

(Ports, GPIF, slave FIFOs)

 

 

 

 

 

 

 

 

 

 

E602

1

PINFLAGSAB[11]

Slave FIFO FLAGA and

FLAGB3

FLAGB2

FLAGB1

FLAGB0

FLAGA3

FLAGA2

FLAGA1

FLAGA0

00000000

RW

 

 

 

FLAGB Pin Configuration

 

 

 

 

 

 

 

 

 

 

E603

1

PINFLAGSCD[11]

Slave FIFO FLAGC and

FLAGD3

FLAGD2

FLAGD1

FLAGD0

FLAGC3

FLAGC2

FLAGC1

FLAGC0

00000000

RW

 

 

 

FLAGD Pin Configuration

 

 

 

 

 

 

 

 

 

 

E604

1

FIFORESET[11]

Restore FIFOS to default

NAKALL

0

0

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

 

 

 

state

 

 

 

 

 

 

 

 

 

 

 

E605

1

BREAKPT

Breakpoint Control

0

0

0

0

BREAK

BPPULSE

BPEN

0

00000000

rrrrbbbr

E606

1

BPADDRH

Breakpoint Address H

A15

A14

A13

A12

A11

A10

A9

A8

xxxxxxxx

RW

E607

1

BPADDRL

Breakpoint Address L

A7

A6

A5

A4

A3

A2

A1

A0

xxxxxxxx

RW

E608

1

UART230

230 Kbaud internally

0

0

0

0

0

0

230UART1

230UART0

00000000

rrrrrrbb

 

 

 

generated ref. clock

 

 

 

 

 

 

 

 

 

 

E609

1

FIFOPINPOLAR[11]

Slave FIFO Interface pins

0

0

PKTEND

SLOE

SLRD

SLWR

EF

FF

00000000

rrbbbbbb

 

 

 

polarity

 

 

 

 

 

 

 

 

 

 

 

E60A

1

REVID

Chip Revision

rv7

rv6

rv5

rv4

rv3

rv2

rv1

rv0

RevA

R

 

 

 

 

 

 

 

 

 

 

 

 

 

00000001

 

E60B

1

REVCTL[11]

Chip Revision Control

0

0

0

0

0

0

dyn_out

enh_pkt

00000000

rrrrrrbb

 

 

UDMA

 

 

 

 

 

 

 

 

 

 

 

 

E60C

1

GPIFHOLDAMOUNT

MSTB Hold Time

0

0

0

0

0

0

HOLDTIME1

HOLDTIME0

00000000

rrrrrrbb

 

 

 

(for UDMA)

 

 

 

 

 

 

 

 

 

 

 

3

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ENDPOINT CONFIGURATION

 

 

 

 

 

 

 

 

 

 

 

E610

1

EP1OUTCFG

Endpoint

1-OUT

VALID

0

TYPE1

TYPE0

0

0

0

0

10100000

brbbrrrr

 

 

 

Configuration

 

 

 

 

 

 

 

 

 

 

E611

1

EP1INCFG

Endpoint

1-IN

VALID

0

TYPE1

TYPE0

0

0

0

0

10100000

brbbrrrr

 

 

 

Configuration

 

 

 

 

 

 

 

 

 

 

E612

1

EP2CFG

Endpoint

2 Configuration

VALID

DIR

TYPE1

TYPE0

SIZE

0

BUF1

BUF0

10100010

bbbbbrbb

E613

1

EP4CFG

Endpoint

4 Configuration

VALID

DIR

TYPE1

TYPE0

0

0

0

0

10100000

bbbbrrrr

E614

1

EP6CFG

Endpoint

6 Configuration

VALID

DIR

TYPE1

TYPE0

SIZE

0

BUF1

BUF0

11100010

bbbbbrbb

E615

1

EP8CFG

Endpoint

8 Configuration

VALID

DIR

TYPE1

TYPE0

0

0

0

0

11100000

bbbbrrrr

 

2

reserved

 

 

 

 

 

 

 

 

 

 

 

 

E618

1

EP2FIFOCFG[11]

Endpoint

2 / slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

 

 

 

configuration

 

 

 

 

 

 

 

 

 

 

E619

1

EP4FIFOCFG[11]

Endpoint

4 / slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

 

 

 

configuration

 

 

 

 

 

 

 

 

 

 

E61A

1

EP6FIFOCFG[11]

Endpoint

6 / slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

 

 

 

configuration

 

 

 

 

 

 

 

 

 

 

E61B

1

EP8FIFOCFG[11]

Endpoint

8 / slave FIFO

0

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN

0

WORDWIDE

00000101

rbbbbbrb

 

 

 

configuration

 

 

 

 

 

 

 

 

 

 

E61C

4

reserved

 

 

 

 

 

 

 

 

 

 

 

 

E620

1

EP2AUTOINLENH[11

Endpoint

2 AUTOIN

0

0

0

0

0

PL10

PL9

PL8

00000010

rrrrrbbb

 

 

 

Packet Length H

 

 

 

 

 

 

 

 

 

 

E621

1

EP2AUTOINLENL[11]

Endpoint

2 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

 

 

 

Packet Length L

 

 

 

 

 

 

 

 

 

 

E622

1

EP4AUTOINLENH[11]

Endpoint

4 AUTOIN

0

0

0

0

0

0

PL9

PL8

00000010

rrrrrrbb

 

 

 

Packet Length H

 

 

 

 

 

 

 

 

 

 

E623

1

EP4AUTOINLENL[11]

Endpoint

4 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

 

 

 

Packet Length L

 

 

 

 

 

 

 

 

 

 

E624

1

EP6AUTOINLENH[11]

Endpoint

6 AUTOIN

0

0

0

0

0

PL10

PL9

PL8

00000010

rrrrrbbb

 

 

 

Packet Length H

 

 

 

 

 

 

 

 

 

 

E625

1

EP6AUTOINLENL[11]

Endpoint

6 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

 

 

 

Packet Length L

 

 

 

 

 

 

 

 

 

 

E626

1

EP8AUTOINLENH[11]

Endpoint

8 AUTOIN

0

0

0

0

0

0

PL9

PL8

00000010

rrrrrrbb

 

 

 

Packet Length H

 

 

 

 

 

 

 

 

 

 

E627

1

EP8AUTOINLENL[11]

Endpoint

8 AUTOIN

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000

RW

 

 

 

Packet Length L

 

 

 

 

 

 

 

 

 

 

E628

1

ECCCFG

ECC Configuration

0

0

0

0

0

0

0

ECCM

00000000

rrrrrrrb

E629

1

ECCRESET

ECC Reset

x

x

x

x

x

x

x

x

00000000

W

E62A

1

ECC1B0

ECC1 Byte 0 Address

LINE15

LINE14

LINE13

LINE12

LINE11

LINE10

LINE9

LINE8

00000000

R

Note

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11. Read and writes to these registers may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”

 

 

Document #: 38-08032 Rev. *L

 

 

 

 

 

 

 

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Contents Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16AFeatures CY7C68015A/16A only Logic Block DiagramFeatures CY7C68013A/14A only Functional Overview ApplicationsBus-powered Applications USB Boot MethodsReNumeration Interrupt SystemFIFO/GPIF Interrupt INT4 INT2 USB InterruptsPriority INT2VEC Value Source Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionInternal Code Memory, EA = Inside FX2LP Outside FX2LPExternal Code Memory, EA = Register AddressesEndpoint Configurations High -speed Mode Setup Data BufferEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytesMaster/Slave Control Signals 12.5 Default Full-Speed Alternate SettingsExternal Fifo Interface ArchitectureECC Generation7 Autopointer AccessGpif USB Uploads and DownloadsCompatible with Previous Generation EZ-USB FX2 18 I2C ControllerPart Number Conversion Table Package Description20 CY7C68013A/14A and CY7C68015A/16A Differences Pin AssignmentsIfclk PE0 PE1128 Pin Tqfp CY7C68013A/CY7C68014ACY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin SsopCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type DefaultPort 56 VF Name Type Default DescriptionFX2LP Pin Descriptions WU2 IFCONFIG1..0FIFOADR0 FIFOADR1PORTCCFG.0 GPIFADR0GPIFADR1 PORTCCFG.1T0OUT Port ET1OUT T2OUTINT6 RXD1OUTT2EX GPIFADR8Flagc FlagbCTL3 CTL4Ground FX2LP Register Summary Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Absolute Maximum Ratings Thermal CharacteristicsOperating Conditions ΘJc + θCaUSB Transceiver DC CharacteristicsAC Electrical Characteristics Program Memory Read Parameters Description Min Typ Max Unit Program Memory ReadClkout Data Memory Read Parameters Description Min Typ Max Unit Data Memory ReadCLKOUT17 Data Memory Write Parameters Description Min Max Unit Data Memory WriteStretch = WR# Strobe Function when Portc is Accessed by Portc Strobe Feature TimingsGpif Synchronous Signals Timing Diagram20 Gpif Synchronous SignalsSlave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Synchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSingle and Burst Synchronous Read Example Sequence Diagram10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous WriteIdeal for non-battery powered applications Ideal for battery powered applicationsOrdering Information Development Tool KitLead Shrunk Small Outline Package O56 Package DiagramsLead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesIssue Orig. Description of Change Date Pyrs Cmcc

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.