Cypress CY7C68013A USB Boot Methods, ReNumeration, Bus-powered Applications, Interrupt System

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CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 1. Special Function Registers

x

8x

9x

Ax

Bx

Cx

Dx

Ex

Fx

0

IOA

IOB

IOC

IOD

SCON1

PSW

ACC

B

1

SP

EXIF

INT2CLR

IOE

SBUF1

 

 

 

2

DPL0

MPAGE

INT4CLR

OEA

 

 

 

 

3

DPH0

 

 

OEB

 

 

 

 

4

DPL1

 

 

OEC

 

 

 

 

5

DPH1

 

 

OED

 

 

 

 

6

DPS

 

 

OEE

 

 

 

 

7

PCON

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

TCON

SCON0

IE

IP

T2CON

EICON

EIE

EIP

9

TMOD

SBUF0

 

 

 

 

 

 

A

TL0

AUTOPTRH1

EP2468STAT

EP01STAT

RCAP2L

 

 

 

B

TL1

AUTOPTRL1

EP24FIFOFLGS

GPIFTRIG

RCAP2H

 

 

 

C

TH0

reserved

EP68FIFOFLGS

 

TL2

 

 

 

D

TH1

AUTOPTRH2

 

GPIFSGLDATH

TH2

 

 

 

E

CKCON

AUTOPTRL2

 

GPIFSGLDATLX

 

 

 

 

F

 

reserved

AUTOPTRSET-UP

GPIFSGLDATLNOX

 

 

 

 

3.5 USB Boot Methods

During the power up sequence, internal logic checks the I2C port for the connection of an EEPROM whose first byte is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0), or it boot-loads the EEPROM contents into internal RAM (0xC2). If no EEPROM is detected, FX2LP enumerates using internally stored descriptors. The default ID values for FX2LP are VID/PID/DID (0x04B4, 0x8613, 0xAxxx where xxx = Chip revision).[2]

Table 2. Default ID Values for FX2LP

 

Default VID/PID/DID

Vendor ID

0x04B4

Cypress Semiconductor

Product ID

0x8613

EZ-USB FX2LP

Device release

0xAnnn

Depends on chip revision

 

 

(nnn = chip revision where first

 

 

silicon = 001)

3.6 ReNumeration™

Because the FX2LP’s configuration is soft, one chip can take on the identities of multiple distinct USB devices.

When first plugged into USB, the FX2LP enumerates automati- cally and downloads firmware and USB descriptor tables over the USB cable. Next, the FX2LP enumerates again, this time as a device defined by the downloaded information. This patented two step process called ReNumeration™ happens instantly when the device is plugged in, without a hint that the initial download step has occurred.

Two control bits in the USBCS (USB Control and Status) register, control the ReNumeration process: DISCON and RENUM. To simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0.

Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device handles device requests over endpoint zero: if RENUM = 0, the Default USB Device handles device requests; if RENUM = 1, the firmware services the requests.

3.7 Bus-powered Applications

The FX2LP fully supports bus powered designs by enumerating with less than 100 mA as required by the USB 2.0 specification.

3.8 Interrupt System

3.8.1 INT2 Interrupt Request and Enable Registers

FX2LP implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See EZ-USB Technical Reference Manual (TRM) for more details.

3.8.2 USB Interrupt Autovectors

The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that is required to identify the individual USB interrupt source, the FX2LP provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the FX2LP pushes the program counter onto its stack then jumps to the address 0x0043 where it expects to find a “jump” instruction to the USB Interrupt service routine.

Note

2. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.

Document #: 38-08032 Rev. *L

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Contents Features CY7C68013A/14A/15A/16A Cypress Semiconductor Corporation 198 Champion CourtFeatures CY7C68013A/14A only Logic Block DiagramFeatures CY7C68015A/16A only Applications Functional OverviewUSB Boot Methods Bus-powered ApplicationsReNumeration Interrupt SystemPriority INT2VEC Value Source INT2 USB InterruptsFIFO/GPIF Interrupt INT4 Reset and Wakeup Reset PinReset Timing Values Condition Program/Data RAMInside FX2LP Outside FX2LP Internal Code Memory, EA =Register Addresses External Code Memory, EA =Setup Data Buffer Endpoint Configurations High -speed ModeEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytes12.5 Default Full-Speed Alternate Settings Master/Slave Control SignalsExternal Fifo Interface ArchitectureAutopointer Access ECC Generation7Gpif USB Uploads and Downloads18 I2C Controller Compatible with Previous Generation EZ-USB FX2Part Number Conversion Table Package DescriptionPin Assignments 20 CY7C68013A/14A and CY7C68015A/16A DifferencesIfclk PE0 PE1128 CY7C68013A/CY7C68014A Pin TqfpCY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop CY7C68013A/CY7C68014A 56-pin Ssop Pin AssignmentCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View FX2LP Pin Descriptions 128 100 56 VF Name Type Default CY7C68013A/15A Pin DescriptionsFX2LP Pin Descriptions 56 VF Name Type Default DescriptionPort IFCONFIG1..0 WU2FIFOADR0 FIFOADR1GPIFADR0 PORTCCFG.0GPIFADR1 PORTCCFG.1Port E T0OUTT1OUT T2OUTRXD1OUT INT6T2EX GPIFADR8Flagb FlagcCTL3 CTL4Ground Register Summary FX2LP Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Thermal Characteristics Absolute Maximum RatingsOperating Conditions ΘJc + θCaAC Electrical Characteristics DC CharacteristicsUSB Transceiver Clkout Program Memory ReadProgram Memory Read Parameters Description Min Typ Max Unit CLKOUT17 Data Memory ReadData Memory Read Parameters Description Min Typ Max Unit Stretch = Data Memory WriteData Memory Write Parameters Description Min Max Unit Portc Strobe Feature Timings WR# Strobe Function when Portc is Accessed byGpif Synchronous Signals Gpif Synchronous Signals Timing Diagram20Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataFIFOADR10 to SLRD/SLWR/PKTEND Setup Time Slave Fifo Synchronous AddressSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSequence Diagram Single and Burst Synchronous Read Example10.17.2 Single and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Read Sequence and Timing Diagram20Sequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram20Ideal for battery powered applications Ideal for non-battery powered applicationsOrdering Information Development Tool KitPackage Diagrams Lead Shrunk Small Outline Package O56Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 PCB Layout Recommendations Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56Quad Flat Package No Leads QFN Package Design Notes Cross-section of the Area Underneath the QFN PackageIssue Orig. Description of Change Date Cmcc Pyrs

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.
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