Cypress CY7C68013A manual Program/Data RAM, Reset Timing Values Condition

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CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 2. Reset Timing Plots

RESET#

RESET#

 

VIL

 

3.3V

 

3.0V

VCC

VCC

 

0V

 

TRESET

Power on Reset

VIL

3.3V

0V

TRESET

Powered Reset

Table 5. Reset Timing Values

Condition

TRESET

Power on Reset with Crystal

5 ms

 

 

Power on Reset with External

200 μs + Clock stability time

Clock

 

Powered Reset

200 μs

 

 

3.9.2 Wakeup Pins

The 8051 puts itself and the rest of the chip into a power down mode by setting PCON.0 = 1. This stops the oscillator and PLL. When WAKEUP is asserted by external logic the oscillator restarts after the PLL stabilizes, and the 8051 receives a wakeup interrupt. This applies whether or not FX2LP is connected to the USB.

The FX2LP exits the power down (USB suspend) state using one of the following methods:

■USB bus activity (if D+/D– lines are left floating, noise on these lines may indicate activity to the FX2LP and initiate a wakeup)

■External logic asserts the WAKEUP pin

■External logic asserts the PA3/WU2 pin

The second wakeup pin, WU2, can also be configured as a general purpose IO pin. This enables a simple external R-C network to be used as a periodic wakeup source. WAKEUP is by default active LOW.

3.10 Program/Data RAM

3.10.1 Size

The FX2LP has 16 KBytes of internal program/data RAM, where PSEN#/RD# signals are internally ORed to enable the 8051 to access it as both program and data memory. No USB control registers appear in this space.

Two memory maps are shown in the following diagrams: Figure 3 on page 8 shows the Internal Code Memory, EA = 0 Figure 4 on page 9 shows the External Code Memory, EA = 1.

3.10.2 Internal Code Memory, EA = 0

This mode implements the internal 16 KByte block of RAM (starting at 0) as combined code and data memory. When external RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This enables the user to connect a 64 KByte memory without requiring address decodes to keep clear of internal memory spaces.

Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM spaces have the following access:

■USB download

■USB upload

■Setup data pointer

■I2C interface boot load.

3.10.3 External Code Memory, EA = 1

The bottom 16 KBytes of program memory is external and therefore the bottom 16 KBytes of internal RAM is accessible only as a data memory.

Document #: 38-08032 Rev. *L

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Contents Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16AFeatures CY7C68013A/14A only Logic Block DiagramFeatures CY7C68015A/16A only Functional Overview ApplicationsInterrupt System USB Boot MethodsBus-powered Applications ReNumerationPriority INT2VEC Value Source INT2 USB InterruptsFIFO/GPIF Interrupt INT4 Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionInternal Code Memory, EA = Inside FX2LP Outside FX2LPExternal Code Memory, EA = Register AddressesSize × 64 bytes Endpoints 0 × 512 bytes Setup Data BufferEndpoint Configurations High -speed Mode Endpoint RAMArchitecture 12.5 Default Full-Speed Alternate SettingsMaster/Slave Control Signals External Fifo InterfaceUSB Uploads and Downloads Autopointer AccessECC Generation7 GpifPackage Description 18 I2C ControllerCompatible with Previous Generation EZ-USB FX2 Part Number Conversion TablePE1 Pin Assignments20 CY7C68013A/14A and CY7C68015A/16A Differences Ifclk PE0128 Pin Tqfp CY7C68013A/CY7C68014ACY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin SsopCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type DefaultFX2LP Pin Descriptions 56 VF Name Type Default DescriptionPort FIFOADR1 IFCONFIG1..0WU2 FIFOADR0PORTCCFG.1 GPIFADR0PORTCCFG.0 GPIFADR1T2OUT Port ET0OUT T1OUTGPIFADR8 RXD1OUTINT6 T2EXCTL4 FlagbFlagc CTL3Ground FX2LP Register Summary Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit ΘJc + θCa Thermal CharacteristicsAbsolute Maximum Ratings Operating ConditionsAC Electrical Characteristics DC CharacteristicsUSB Transceiver Clkout Program Memory ReadProgram Memory Read Parameters Description Min Typ Max Unit CLKOUT17 Data Memory ReadData Memory Read Parameters Description Min Typ Max Unit Stretch = Data Memory WriteData Memory Write Parameters Description Min Max Unit WR# Strobe Function when Portc is Accessed by Portc Strobe Feature TimingsGpif Synchronous Signals Timing Diagram20 Gpif Synchronous SignalsSlave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableRD/WR/PKTEND to FIFOADR10 Hold Time FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressSingle and Burst Synchronous Read Example Sequence Diagram10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous WriteDevelopment Tool Kit Ideal for battery powered applicationsIdeal for non-battery powered applications Ordering InformationLead Shrunk Small Outline Package O56 Package DiagramsLead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesIssue Orig. Description of Change Date Pyrs Cmcc

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.
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