Arm Enterprises IM-AD1 manual ADC and DAC interfaces, ADC and DAC interface architecture

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Hardware Reference

3.8ADC and DAC interfaces

The interface module provides two A to D Converters (ADC) and a D to A Converter (DAC). The two ADCs each provide eight analog inputs with buffered 0-5V inputs, an internal multiplexer, and a 12-bit converter. The ADCs provide a 16-bit host interface with conversion data appearing on D[11:0] (and zeros on D[15:12]). The ADCs are clocked by a 4MHz crystal and are able to perform 200ksamples/s.

The DAC provides two 0-5V outputs with a 12-bit resolution.

The ADCs and DAC are powered from a 5V supply and share buffers to interface them to the 3.3V system bus provided by the logic module.

Figure 3-10shows the architecture of the ADCs and DACs.

 

AD_T/R

Buffers

AD_D[15:0]_5V

 

AD_nOE

(U5U13

 

 

AD_D[15:0]

and

 

 

 

U8)

ADC

 

ADC1_CONV

 

 

 

(U6)

 

ADC1_nCS

 

 

 

ADC1_BUSY_5V

 

ADC1_nWR

 

 

 

 

 

ADC1_RD

 

 

 

ADC2_CONV

 

 

socket

ADC2_nCS

 

 

ADC2_nWR

 

 

ADC2_RD

 

ADC

EXPIM

 

 

ADC1_BUSY

 

(U10)

ADC2_BUSY

Buffer

ADC2_BUSY_5V

 

ADC_CLK

(U7)

ADC_CLK_5V

 

 

 

XTAL

 

 

 

(U12)

DAC_nCLR

 

 

 

 

 

 

DAC_nLDAC

 

 

DAC

DAC_A0

 

 

(U11)

DAC_nCS

 

 

 

DAC_nWR

 

 

 

AIN[7:0]

AIN[8:15]

Buffers

(U1 and U2

Buffers

(U3 and U4)

J1

J2

Figure 3-10 ADC and DAC interface architecture

All of the interface signals are routed to the FPGA on the logic module. The ADCs and DAC are supported by an AHB interface that is instantiated in the logic module code example supplied with the IM-AD1.

3-18

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

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Contents Integrator/IM-AD1 Integrator/IM-AD1 User GuideConformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter IntroductionAppendix a Signal Descriptions Preface Using this book About this bookIntended audience Typographical conventions Further readingARM publications Third-party documents Feedback Feedback on this documentFeedback on the Integrator/IM-AD1 Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163BIntegrator/IM-AD1 layout Interface module features and architecture FeaturesIntegrator/IM-AD1 block diagram ArchitectureConfig LED Links and LEDsCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development systemSetting up the logic module Switch 2 Closed Switch 3 Open Switch 4 OpenRunning the test software Hardware Reference Hardware Reference Uart interface Serial interface signal assignment Signal nameConnector DescriptionSerial connector pinout Serial connector signal assignment Pin J18 Type DescriptionSPI signals Signal SPIPWM interface signals Signal PWM interfaceShows the signal assignment PWM connector signals Pin J14 J10 DescriptionStepper motor interface Functional descriptionStepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fittedStepper motor connectors Stepper motor interface signalsStepper motor connector signals Pin J19 J23 Description VSSGpio connectors J16 and J17 GpioHardware Reference Can interface U13Buffer Can interface signal assignment Signal IMBBANK28 IMBBANK29IMBBANK30 Can connector signal assignments Pin GNDADC and DAC interfaces 10 ADC and DAC interface architectureIMABANK50 IMABANK48IMABANK49 IMABANK5111shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About the design example About PrimeCellsExample architecture Vhdl file descriptions File DescriptionExample memory map Address assignment of logic modules Integrator system memory mapIntegrator/IM-AD1 memory map Logic module addresses Position Bits StackIntegrator/IM-AD1 memory map Device Address Gpiob StepperbGpioa SsramExample APB register peripheral Logic module registersOffset address Name Type Function Oscillator divisor registers LMOSCx registers Bits Name Access Function RDWVDW User LEDs control register Bits Name Access FunctionOscillator lock register Push button interrupt registerSwitches register Uart SPICS1 SPI chip select registerSPICS2 SPICS0Synchronous serial port PWM controller Cont Offset Name Access Function AddressStepper motor peripheral CountStepper x control register Docount SinglestepDIR Stepx count register Stepx speed registerData output set register Read data output pinsAddress offset Name Access Size Function Read data input registerData direction Gpio direction control 1 bitSsram interface Interrupt Interrupt source Source number Vectored interrupt controllerInterrupt sources CAN1Reference Design Example Can controller interface Can reset control registerCanreset CANxBaseAdcstatus ADC and DAC interface16 ADC and DAC interface registers ADC2BUSYPeripheral information block 18 PIB entry formatBits Name Function Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal DescriptionExpb Table A-2 Expb signal description Pin label Name DescriptionExpim Table A-3 Expim signal descriptions LabelLM-EP20K1000E Description Logic analyzer connector Figure A-4 J7 pin locationsTable A-4 J7 connector pinout Signal Pin CLK1Figure A-5 Multi-ICE connector pinout Multi-ICE JtagMechanical Specification Figure B-1 Board dimensions top view Mechanical informationFigure B-2 Bottom board dimensions viewed from top side Connector reference DB9DUALDB9STRAIGHT FCI Glossary Multi-ICESynchronous Serial Port DAC IndexADC Can GpioExpa A-2 Gpiodataclr Gpiodatain Gpiodataout Gpiodataset GpiodirnLmleds Lmlock LMOSC1