Arm Enterprises IM-AD1 Table A-3 Expim signal descriptions, Label, LM-EP20K1000E Description

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Signal Descriptions

Table A-3 shows the signals for the interface module for Integrator/LM-XCV2000E or LM-EP20K1000E logic module types.

			Table A-3 EXPIM signal descriptions

Label	LM-XCV2000E	LM-EP20K1000E	Description

IM_ABANK[59:0]	IM_0BANK[59:0]	IM_5BANK[59:0]	FPGA input/output pins.

IM_BBANK[53:0]	IM_1BANK[53:0]	IM_6BANK[53:0]	FPGA input/output pins.

EXP[92:85]	Not used	Not used	-

EXP93	IM_CLK	IM_CLK	Clock signal from IM-AD1 to the logic module
			FPGA.

EXP[96:94]	Not used	Not used	-

EXP97	VCCO_0	VCCO_5	Configurable voltage power supply rail.
			Not used (socket).

EXP98	VCCO_0	VCCO_5	Configurable voltage power supply rail.
			Not used (socket).

EXP185	Not used	Not used	-

EXP[189:187]	Not used	Not used	-

EXP191	CLK1_1	CLK1_1	Clock signal from the CLK1 buffer on the logic
			module

EXP194	GND	GND	Ground

EXP[196:192]	Not used	Not used	-

EXP197	VCCO_1	VCCO_6	Configurable voltage power supply rail.
			Not used (socket).

EXP198	VCCO_1	VCCO_6	Configurable voltage power supply rail
			Not used (socket).

Caution

For correct operation of the interface module, VCCO_A and VCCO_B must be set to 3.3V. Ensure that the VCCO links are set correctly on the logic module.

ARM DUI 0163B

Copyright © 2001-2003. All rights reserved.

A-7

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Contents Integrator/IM-AD1 User Guide Integrator/IM-AD1Conformance Notices Copyright 2001-2003. All rights reserved Chapter Introduction Integrator/IM-AD1 User GuideAppendix a Signal Descriptions Preface Using this book About this bookIntended audience Typographical conventions Further readingARM publications Third-party documents Feedback Feedback on this documentFeedback on the Integrator/IM-AD1 Xii Introduction ARM DUI 0163B About the Integrator/IM-AD1Integrator/IM-AD1 layout Features Interface module features and architectureArchitecture Integrator/IM-AD1 block diagramLinks and LEDs Config LEDCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Assembled Integrator development system Fitting the interface moduleSwitch 2 Closed Switch 3 Open Switch 4 Open Setting up the logic moduleRunning the test software Hardware Reference Hardware Reference Connector Serial interface signal assignment Signal nameUart interface DescriptionSerial connector signal assignment Pin J18 Type Description Serial connector pinoutSPI SPI signals SignalPWM interface PWM interface signals SignalPWM connector signals Pin J14 J10 Description Shows the signal assignmentFunctional description Stepper motor interfaceTherefore, with a 0.1Ω sense resistor fitted Stepper motor interface signal summaryStepper motor interface signals Stepper motor connectorsVSS Stepper motor connector signals Pin J19 J23 DescriptionGpio Gpio connectors J16 and J17Hardware Reference Can interface U13Buffer Can interface signal assignment Signal IMBBANK28 IMBBANK29IMBBANK30 GND Can connector signal assignments Pin10 ADC and DAC interface architecture ADC and DAC interfacesIMABANK49 IMABANK48IMABANK50 IMABANK5111shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About the design example About PrimeCellsExample architecture File Description Vhdl file descriptionsExample memory map Integrator system memory map Address assignment of logic modulesIntegrator/IM-AD1 memory map Logic module addresses Position Bits StackIntegrator/IM-AD1 memory map Device Address Gpioa StepperbGpiob SsramExample APB register peripheral Logic module registersOffset address Name Type Function Oscillator divisor registers LMOSCx registers Bits Name Access Function RDWVDW Oscillator lock register Bits Name Access FunctionUser LEDs control register Push button interrupt registerSwitches register Uart SPICS2 SPI chip select registerSPICS1 SPICS0Synchronous serial port PWM controller Stepper motor peripheral Offset Name Access Function AddressCont CountStepper x control register Docount SinglestepDIR Stepx speed register Stepx count registerAddress offset Name Access Size Function Read data output pinsData output set register Read data input registerGpio direction control 1 bit Data directionSsram interface Interrupt sources Vectored interrupt controllerInterrupt Interrupt source Source number CAN1Reference Design Example Canreset Can reset control registerCan controller interface CANxBase16 ADC and DAC interface registers ADC and DAC interfaceAdcstatus ADC2BUSYPeripheral information block 18 PIB entry formatBits Name Function Signal Descriptions Expa Pin label Signal Description Table A-1 AHB signal assignmentExpb Pin label Name Description Table A-2 Expb signal descriptionExpim Table A-3 Expim signal descriptions LabelLM-EP20K1000E Description Figure A-4 J7 pin locations Logic analyzer connectorCLK1 Table A-4 J7 connector pinout Signal PinMulti-ICE Jtag Figure A-5 Multi-ICE connector pinoutMechanical Specification Mechanical information Figure B-1 Board dimensions top viewFigure B-2 Bottom board dimensions viewed from top side Connector reference DB9DUALDB9STRAIGHT FCI Multi-ICE GlossarySynchronous Serial Port ADC Can IndexDAC GpioExpa A-2 Gpiodataclr Gpiodatain Gpiodataout Gpiodataset GpiodirnLmleds Lmlock LMOSC1