Arm Enterprises IM-AD1 manual Peripheral information block, PIB entry format, Bits Name Function

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Reference Design Example

4.13Peripheral information block

The Peripheral Information Block (PIB) is a block of 32 words in ROM that provides you with information about the peripherals used in the design. The PIB is located at the top of the address space for the logic module.

Each word in the PIB provides information about one peripheral. A value of 0x00000000 indicates that there is no entry and that the next address must be checked. Each valid entry contains the information shown in Table 4-18.

 

 

Table 4-18 PIB entry format

 

 

 

Bits

Name

Function

 

 

 

31:24

Peripheral Base

Bits [27:20] of the peripheral base address.

 

 

Bits [31:28] of the address are defined by the location of

 

 

the logic module in the stack see Address assignment of

 

 

logic modules on page 4-5.

 

 

 

23:8

Peripheral ID

For a PrimeCell, this is the PrimeCell number in BCD. For

 

 

example, the VIC PrimeCell PL190 would be represented

 

 

by 0x0190.

 

 

For other peripherals the value 0xFFnn is assigned, where

 

 

nn is a unique look-up value. (See the AHBPIB HDL

 

 

source file for details.) The value 0xFFFF is a special case

 

 

that is used to indicate the FPGA build number.

 

 

 

7:0

Peripheral Rev

This gives the revision number of the peripheral in BCD.

 

 

For example, revision v1.2 is represented by 0x12.

 

 

 

The last address of the PIB is used to store the FPGA build number. Bits [31:8] are all 1 and bits [7:0] store the revision number in BCD.

Note

Use the ARM executable utility read_pib.axf, supplied on the IM-AD1 CD, to display the PIB information.

4-28

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

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Contents Integrator/IM-AD1 Integrator/IM-AD1 User GuideConformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter IntroductionAppendix a Signal Descriptions Preface Intended audience Using this bookAbout this book ARM publications Typographical conventionsFurther reading Third-party documents Feedback on the Integrator/IM-AD1 FeedbackFeedback on this document Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163BIntegrator/IM-AD1 layout Interface module features and architecture FeaturesIntegrator/IM-AD1 block diagram ArchitectureConfig LED Links and LEDsCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development systemSetting up the logic module Switch 2 Closed Switch 3 Open Switch 4 OpenRunning the test software Hardware Reference Hardware Reference Uart interface Serial interface signal assignment Signal nameConnector DescriptionSerial connector pinout Serial connector signal assignment Pin J18 Type DescriptionSPI signals Signal SPIPWM interface signals Signal PWM interfaceShows the signal assignment PWM connector signals Pin J14 J10 DescriptionStepper motor interface Functional descriptionStepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fittedStepper motor connectors Stepper motor interface signalsStepper motor connector signals Pin J19 J23 Description VSSGpio connectors J16 and J17 GpioHardware Reference Buffer Can interfaceU13 Can interface signal assignment Signal IMBBANK30 IMBBANK28IMBBANK29 Can connector signal assignments Pin GNDADC and DAC interfaces 10 ADC and DAC interface architectureIMABANK50 IMABANK48IMABANK49 IMABANK5111shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example Example architecture About the design exampleAbout PrimeCells Vhdl file descriptions File DescriptionExample memory map Address assignment of logic modules Integrator system memory mapIntegrator/IM-AD1 memory map Device Address Integrator/IM-AD1 memory mapLogic module addresses Position Bits Stack Gpiob StepperbGpioa SsramOffset address Name Type Function Example APB register peripheralLogic module registers Oscillator divisor registers VDW LMOSCx registers Bits Name Access FunctionRDW User LEDs control register Bits Name Access FunctionOscillator lock register Push button interrupt registerSwitches register Uart SPICS1 SPI chip select registerSPICS2 SPICS0Synchronous serial port PWM controller Cont Offset Name Access Function AddressStepper motor peripheral CountStepper x control register DIR DocountSinglestep Stepx count register Stepx speed registerData output set register Read data output pinsAddress offset Name Access Size Function Read data input registerData direction Gpio direction control 1 bitSsram interface Interrupt Interrupt source Source number Vectored interrupt controllerInterrupt sources CAN1Reference Design Example Can controller interface Can reset control registerCanreset CANxBaseAdcstatus ADC and DAC interface16 ADC and DAC interface registers ADC2BUSYBits Name Function Peripheral information block18 PIB entry format Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal DescriptionExpb Table A-2 Expb signal description Pin label Name DescriptionExpim LM-EP20K1000E Description Table A-3 Expim signal descriptionsLabel Logic analyzer connector Figure A-4 J7 pin locationsTable A-4 J7 connector pinout Signal Pin CLK1Figure A-5 Multi-ICE connector pinout Multi-ICE JtagMechanical Specification Figure B-1 Board dimensions top view Mechanical informationFigure B-2 Bottom board dimensions viewed from top side DB9STRAIGHT FCI Connector referenceDB9DUAL Glossary Multi-ICESynchronous Serial Port DAC IndexADC Can GpioLmleds Lmlock LMOSC1 Expa A-2Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn