Arm Enterprises IM-AD1 manual Gpio connectors J16 and J17

Page 36

Hardware Reference

3.6GPIO

The interface module provides two connectors for GPIO interfaces. Each connector provides 32 GPIO lines connected directly to the logic module FPGA. The connectors are shown in Figure 3-7.

+5V GND GPIOA1 GPIOA2 GPIOA4 GPIOA5 GPIOA7 GPIOA8 GPIOA10 GPIOA11 GPIOA13 GPIOA14 GPIOA16 GPIOA17 GPIOA19 GPIOA20 GPIOA22 GPIOA23 GPIOA25 GPIOA26 GPIOA28 GPIOA29 GPIOA31 +12V +5v

J17

1 2

49 50

+3V3		+5V
GPIOA0		GND
GND		GPIOB1
GPIOA3		GPIOB2
GND		GPIOB4
GPIOA6		GPIOB5
GND		GPIOB7
GPIOA9		GPIOB8
GND		GPIOB10
GPIOA12		GPIOB11
GND		GPIOB13
GPIOA15		GPIOB14
GND		GPIOB16
GPIOA18		GPIOB17
GND		GPIOB19
GPIOA21		GPIOB20
GND		GPIOB22
GPIOA24		GPIOB23
GND		GPIOB25
GPIOA27		GPIOB26
GND		GPIOB28
GPIOA30		GPIOB29
GND		GPIOB31
-12V		+12V
+3V3		+5v
		+5v

J16

1 2

49 50

+3V3

GPIOB0 GND GPIOB3 GND GPIOB6 GND GPIOB9 GND GPIOB12

GND GPIOB15

GND GPIOB18

GND GPIOB21

GND GPIOB24

GND GPIOB27

GND GPIOB30

GND -12V +3V3

Figure 3-7 GPIO connectors J16 and J17

3-12

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

Image 36

Contents Integrator/IM-AD1 Integrator/IM-AD1 User GuideConformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter IntroductionAppendix a Signal Descriptions Preface Using this book About this bookIntended audience Typographical conventions Further readingARM publications Third-party documents Feedback Feedback on this documentFeedback on the Integrator/IM-AD1 Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163BIntegrator/IM-AD1 layout Interface module features and architecture FeaturesIntegrator/IM-AD1 block diagram ArchitectureConfig LED Links and LEDsCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development systemSetting up the logic module Switch 2 Closed Switch 3 Open Switch 4 OpenRunning the test software Hardware Reference Hardware Reference Serial interface signal assignment Signal name ConnectorUart interface DescriptionSerial connector pinout Serial connector signal assignment Pin J18 Type DescriptionSPI signals Signal SPIPWM interface signals Signal PWM interfaceShows the signal assignment PWM connector signals Pin J14 J10 DescriptionStepper motor interface Functional descriptionStepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fittedStepper motor connectors Stepper motor interface signalsStepper motor connector signals Pin J19 J23 Description VSSGpio connectors J16 and J17 GpioHardware Reference Can interface U13Buffer Can interface signal assignment Signal IMBBANK28 IMBBANK29IMBBANK30 Can connector signal assignments Pin GNDADC and DAC interfaces 10 ADC and DAC interface architectureIMABANK48 IMABANK49IMABANK50 IMABANK5111shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About the design example About PrimeCellsExample architecture Vhdl file descriptions File DescriptionExample memory map Address assignment of logic modules Integrator system memory mapIntegrator/IM-AD1 memory map Logic module addresses Position Bits StackIntegrator/IM-AD1 memory map Device Address Stepperb GpioaGpiob SsramExample APB register peripheral Logic module registersOffset address Name Type Function Oscillator divisor registers LMOSCx registers Bits Name Access Function RDWVDW Bits Name Access Function Oscillator lock registerUser LEDs control register Push button interrupt registerSwitches register Uart SPI chip select register SPICS2SPICS1 SPICS0Synchronous serial port PWM controller Offset Name Access Function Address Stepper motor peripheralCont CountStepper x control register Docount SinglestepDIR Stepx count register Stepx speed registerRead data output pins Address offset Name Access Size FunctionData output set register Read data input registerData direction Gpio direction control 1 bitSsram interface Vectored interrupt controller Interrupt sourcesInterrupt Interrupt source Source number CAN1Reference Design Example Can reset control register CanresetCan controller interface CANxBaseADC and DAC interface 16 ADC and DAC interface registersAdcstatus ADC2BUSYPeripheral information block 18 PIB entry formatBits Name Function Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal DescriptionExpb Table A-2 Expb signal description Pin label Name DescriptionExpim Table A-3 Expim signal descriptions LabelLM-EP20K1000E Description Logic analyzer connector Figure A-4 J7 pin locationsTable A-4 J7 connector pinout Signal Pin CLK1Figure A-5 Multi-ICE connector pinout Multi-ICE JtagMechanical Specification Figure B-1 Board dimensions top view Mechanical informationFigure B-2 Bottom board dimensions viewed from top side Connector reference DB9DUALDB9STRAIGHT FCI Glossary Multi-ICESynchronous Serial Port Index ADC CanDAC GpioExpa A-2 Gpiodataclr Gpiodatain Gpiodataout Gpiodataset GpiodirnLmleds Lmlock LMOSC1