Arm Enterprises IM-AD1 manual Vhdl file descriptions, File Description

Page 49

Reference Design Example

System

bus

AHB

Unidirectional to bidirectional AHB interface

Default slave

Address decoder

AHB

to

APB

bridge

PIB

CAN

ADC/DAC

ZBT

SSRAM

controller

VIC

APB

Control

registers

UART

SSP

GPIO A

GPIO B

Stepper A

Stepper B

DC/DC

converter

 

Figure 4-1 Design example architecture

 

Table 4-1provides a summary description of the supplied VHDL files. A more detailed

 

description of each VHDL block is included within the files in the form of comments.

 

Table 4-1 VHDL file descriptions

 

 

File

Description

 

 

IMAD1fpga

This file is the top-level VHDL that instantiates all of the interface for the example. The VHDL for

 

the PrimeCell interfaces are not supplied but are available from ARM as separate products.

 

 

AHBDecoder

The decoder provides the AHB peripherals with select line generated from the address lines and the

 

module ID (position in stack) signals from the motherboard. The Integrator family of boards uses a

 

distributed address decoding system (see Address assignment of logic modules on page 4-5).

 

 

AHBDefaultSlave

This block provides a default slave response when the logic module address space is addressed but

 

the address does not correspond to any of the instantiated peripherals.

ARM DUI 0163B

Copyright © 2001-2003. All rights reserved.

4-3

Image 49
Contents Integrator/IM-AD1 User Guide Integrator/IM-AD1Conformance Notices Copyright 2001-2003. All rights reserved Chapter Introduction Integrator/IM-AD1 User GuideAppendix a Signal Descriptions Preface About this book Using this bookIntended audience Further reading Typographical conventionsARM publications Third-party documents Feedback on this document FeedbackFeedback on the Integrator/IM-AD1 Xii Introduction ARM DUI 0163B About the Integrator/IM-AD1Integrator/IM-AD1 layout Features Interface module features and architectureArchitecture Integrator/IM-AD1 block diagramLinks and LEDs Config LEDCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Assembled Integrator development system Fitting the interface moduleSwitch 2 Closed Switch 3 Open Switch 4 Open Setting up the logic moduleRunning the test software Hardware Reference Hardware Reference Connector Serial interface signal assignment Signal nameUart interface DescriptionSerial connector signal assignment Pin J18 Type Description Serial connector pinoutSPI SPI signals SignalPWM interface PWM interface signals SignalPWM connector signals Pin J14 J10 Description Shows the signal assignmentFunctional description Stepper motor interfaceTherefore, with a 0.1Ω sense resistor fitted Stepper motor interface signal summaryStepper motor interface signals Stepper motor connectorsVSS Stepper motor connector signals Pin J19 J23 DescriptionGpio Gpio connectors J16 and J17Hardware Reference U13 Can interfaceBuffer Can interface signal assignment Signal IMBBANK29 IMBBANK28IMBBANK30 GND Can connector signal assignments Pin10 ADC and DAC interface architecture ADC and DAC interfacesIMABANK49 IMABANK48IMABANK50 IMABANK5111shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About PrimeCells About the design exampleExample architecture File Description Vhdl file descriptionsExample memory map Integrator system memory map Address assignment of logic modulesLogic module addresses Position Bits Stack Integrator/IM-AD1 memory mapIntegrator/IM-AD1 memory map Device Address Gpioa StepperbGpiob SsramLogic module registers Example APB register peripheralOffset address Name Type Function Oscillator divisor registers RDW LMOSCx registers Bits Name Access FunctionVDW Oscillator lock register Bits Name Access FunctionUser LEDs control register Push button interrupt registerSwitches register Uart SPICS2 SPI chip select registerSPICS1 SPICS0Synchronous serial port PWM controller Stepper motor peripheral Offset Name Access Function AddressCont CountStepper x control register Singlestep DocountDIR Stepx speed register Stepx count registerAddress offset Name Access Size Function Read data output pinsData output set register Read data input registerGpio direction control 1 bit Data directionSsram interface Interrupt sources Vectored interrupt controllerInterrupt Interrupt source Source number CAN1Reference Design Example Canreset Can reset control registerCan controller interface CANxBase16 ADC and DAC interface registers ADC and DAC interfaceAdcstatus ADC2BUSY18 PIB entry format Peripheral information blockBits Name Function Signal Descriptions Expa Pin label Signal Description Table A-1 AHB signal assignmentExpb Pin label Name Description Table A-2 Expb signal descriptionExpim Label Table A-3 Expim signal descriptionsLM-EP20K1000E Description Figure A-4 J7 pin locations Logic analyzer connectorCLK1 Table A-4 J7 connector pinout Signal PinMulti-ICE Jtag Figure A-5 Multi-ICE connector pinoutMechanical Specification Mechanical information Figure B-1 Board dimensions top viewFigure B-2 Bottom board dimensions viewed from top side DB9DUAL Connector referenceDB9STRAIGHT FCI Multi-ICE GlossarySynchronous Serial Port ADC Can IndexDAC GpioGpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn Expa A-2Lmleds Lmlock LMOSC1