Arm Enterprises IM-AD1 manual Example memory map

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Reference Design Example

 

 

Table 4-1 VHDL file descriptions (continued)

 

 

File

Description

 

 

AHBMux7S1M

This is the AHB multiplexor that connects the read data buses and the HRESP and HREADY

 

signals from all of the slaves to the AHB master.

 

 

AHBZBTRAM

An SSRAM controller block to support word, halfword, and byte operations to the SSRAM on the

 

logic module.

 

 

AHB2APB

This is the bridge block required to connect APB peripherals to the high-speed AMBA AHB bus.

 

It produces the peripheral select signals for each of the APB peripherals.

 

 

APBRegs

The APB register peripheral provides memory-mapped registers that you can use to:

 

configure the two clock generators (protected by the LM_LOCK register)

 

write to the user LEDs

 

read the user switch inputs

 

produce an interrupt for the LM push button.

 

 

AHBPIB

This provides the ROM block that gives the following information about each peripheral:

 

base address

 

PrimeCell number

 

peripheral revision number

 

FPGA revision number.

 

 

BuildOptions

This file defines generation of the PrimeCells in the example and allows control over the synthesis

 

so that PrimeCells can be included or excluded. It specifies the base address of all the peripherals.

 

 

GPIO32

This is a simple 32-bit GPIO block.

 

 

SPICSReg

This is a simple register that is used to generate the chip selects for the SPI bus.

 

 

AHB2CAN

This is the interface between the AHB and Bosch CC770 CAN devices.

 

 

AHB2AD7859

This is the interface between the AHB and the ADC and DAC converters.

 

 

Stepper

This is the stepper motor controller logic, which has an APB interface.

 

 

 

4.1.3Example memory map

The supplied examples set up the memory map for the logic module as shown in Figure 4-2 on page 4-5. This shows the locations to which logic modules are assigned by the main address decoder on an Integrator/AP motherboard when the logic modules are fitted in the EXPA/EXPB connector positions. The diagram also shows how the example decodes the address space for the logic module when it is LM0 (bottom of the stack).

4-4

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

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Contents Integrator/IM-AD1 Integrator/IM-AD1 User GuideConformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter IntroductionAppendix a Signal Descriptions Preface Intended audience Using this bookAbout this book ARM publications Typographical conventionsFurther reading Third-party documents Feedback on the Integrator/IM-AD1 FeedbackFeedback on this document Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163BIntegrator/IM-AD1 layout Interface module features and architecture FeaturesIntegrator/IM-AD1 block diagram ArchitectureConfig LED Links and LEDsCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development systemSetting up the logic module Switch 2 Closed Switch 3 Open Switch 4 OpenRunning the test software Hardware Reference Hardware Reference Uart interface Serial interface signal assignment Signal nameConnector DescriptionSerial connector pinout Serial connector signal assignment Pin J18 Type DescriptionSPI signals Signal SPIPWM interface signals Signal PWM interfaceShows the signal assignment PWM connector signals Pin J14 J10 DescriptionStepper motor interface Functional descriptionStepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fittedStepper motor connectors Stepper motor interface signalsStepper motor connector signals Pin J19 J23 Description VSSGpio connectors J16 and J17 GpioHardware Reference Buffer Can interfaceU13 Can interface signal assignment Signal IMBBANK30 IMBBANK28IMBBANK29 Can connector signal assignments Pin GNDADC and DAC interfaces 10 ADC and DAC interface architectureIMABANK50 IMABANK48IMABANK49 IMABANK5111shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example Example architecture About the design exampleAbout PrimeCells Vhdl file descriptions File DescriptionExample memory map Address assignment of logic modules Integrator system memory mapIntegrator/IM-AD1 memory map Device Address Integrator/IM-AD1 memory mapLogic module addresses Position Bits Stack Gpiob StepperbGpioa SsramOffset address Name Type Function Example APB register peripheralLogic module registers Oscillator divisor registers VDW LMOSCx registers Bits Name Access FunctionRDW User LEDs control register Bits Name Access FunctionOscillator lock register Push button interrupt registerSwitches register Uart SPICS1 SPI chip select registerSPICS2 SPICS0Synchronous serial port PWM controller Cont Offset Name Access Function AddressStepper motor peripheral CountStepper x control register DIR DocountSinglestep Stepx count register Stepx speed registerData output set register Read data output pinsAddress offset Name Access Size Function Read data input registerData direction Gpio direction control 1 bitSsram interface Interrupt Interrupt source Source number Vectored interrupt controllerInterrupt sources CAN1Reference Design Example Can controller interface Can reset control registerCanreset CANxBaseAdcstatus ADC and DAC interface16 ADC and DAC interface registers ADC2BUSYBits Name Function Peripheral information block18 PIB entry format Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal DescriptionExpb Table A-2 Expb signal description Pin label Name DescriptionExpim LM-EP20K1000E Description Table A-3 Expim signal descriptionsLabel Logic analyzer connector Figure A-4 J7 pin locationsTable A-4 J7 connector pinout Signal Pin CLK1Figure A-5 Multi-ICE connector pinout Multi-ICE JtagMechanical Specification Figure B-1 Board dimensions top view Mechanical informationFigure B-2 Bottom board dimensions viewed from top side DB9STRAIGHT FCI Connector referenceDB9DUAL Glossary Multi-ICESynchronous Serial Port DAC IndexADC Can GpioLmleds Lmlock LMOSC1 Expa A-2Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn