Arm Enterprises IM-AD1 manual ADC and DAC interface registers, Adcstatus, ADC2BUSY, ADC1BUSY

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Reference Design Example

4.12ADC and DAC interface

This interface gives you access to the ADCs and DAC. The interface also contains a status and control register. The offset addresses of the ADC and DAC interface are shown in Table 4-16.

			Table 4-16 ADC and DAC interface registers

	Offset	Name	Function
	address	Name	Function
	address

	0x000000	ADCSTATUS	This register enables you to monitor the status of the ADC
			busy signals

	0x000004	DACnCLR	This register controls the nCLR signal to the DAC.

	0x100000	ADC1Base	Interface to ADC1

	0x200000	ADC2Base	Interface to ADC2

	0x300000	DACBase	Interface to the DAC

The ADCs each appear as one 16-bit location at the corresponding base address. The DAC appears as two locations at DACBase and DACBase+4 that correspond to the DAC A and B channels respectively. Refer to the AD7859 and AD5342 data sheets for details of ADC and DAC operations.

Accesses to these devices take four system bus clock cycles, although consecutive accesses incur an additional three wait states for the second and subsequent access. The DAC has the signal LDAC tied LOW. This means that a value is passed to the DAC as soon as it is written.

The ADC status register provides you with read-only access to the ADC busy signals. The bit assignment is shown in Table 4-17.

Table 4-17 ADC status register bit assignment

Bit	Name	Access	Function

1	ADC2BUSY	Read	Gives value of ADC2 busy signal

0	ADC1BUSY	Read	Gives value of ADC1 busy signal

The DACnCLR register provides you with read/write access to control the signal nCLR routed to the DAC. Write 0 to this register to reset the DAC value to 0. You must write a 1 to enable normal operation of the DAC.

ARM DUI 0163B

Copyright © 2001-2003. All rights reserved.

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Contents Integrator/IM-AD1 User Guide Integrator/IM-AD1Conformance Notices Copyright 2001-2003. All rights reserved Chapter Introduction Integrator/IM-AD1 User GuideAppendix a Signal Descriptions Preface About this book Using this bookIntended audience Further reading Typographical conventionsARM publications Third-party documents Feedback on this document FeedbackFeedback on the Integrator/IM-AD1 Xii Introduction ARM DUI 0163B About the Integrator/IM-AD1Integrator/IM-AD1 layout Features Interface module features and architectureArchitecture Integrator/IM-AD1 block diagramLinks and LEDs Config LEDCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Assembled Integrator development system Fitting the interface moduleSwitch 2 Closed Switch 3 Open Switch 4 Open Setting up the logic moduleRunning the test software Hardware Reference Hardware Reference Connector Serial interface signal assignment Signal nameUart interface DescriptionSerial connector signal assignment Pin J18 Type Description Serial connector pinoutSPI SPI signals SignalPWM interface PWM interface signals SignalPWM connector signals Pin J14 J10 Description Shows the signal assignmentFunctional description Stepper motor interfaceTherefore, with a 0.1Ω sense resistor fitted Stepper motor interface signal summaryStepper motor interface signals Stepper motor connectorsVSS Stepper motor connector signals Pin J19 J23 DescriptionGpio Gpio connectors J16 and J17Hardware Reference U13 Can interfaceBuffer Can interface signal assignment Signal IMBBANK29 IMBBANK28IMBBANK30 GND Can connector signal assignments Pin10 ADC and DAC interface architecture ADC and DAC interfacesIMABANK49 IMABANK48IMABANK50 IMABANK5111shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About PrimeCells About the design exampleExample architecture File Description Vhdl file descriptionsExample memory map Integrator system memory map Address assignment of logic modulesLogic module addresses Position Bits Stack Integrator/IM-AD1 memory mapIntegrator/IM-AD1 memory map Device Address Gpioa StepperbGpiob SsramLogic module registers Example APB register peripheralOffset address Name Type Function Oscillator divisor registers RDW LMOSCx registers Bits Name Access FunctionVDW Oscillator lock register Bits Name Access FunctionUser LEDs control register Push button interrupt registerSwitches register Uart SPICS2 SPI chip select registerSPICS1 SPICS0Synchronous serial port PWM controller Stepper motor peripheral Offset Name Access Function AddressCont CountStepper x control register Singlestep DocountDIR Stepx speed register Stepx count registerAddress offset Name Access Size Function Read data output pinsData output set register Read data input registerGpio direction control 1 bit Data directionSsram interface Interrupt sources Vectored interrupt controllerInterrupt Interrupt source Source number CAN1Reference Design Example Canreset Can reset control registerCan controller interface CANxBase16 ADC and DAC interface registers ADC and DAC interfaceAdcstatus ADC2BUSY18 PIB entry format Peripheral information blockBits Name Function Signal Descriptions Expa Pin label Signal Description Table A-1 AHB signal assignmentExpb Pin label Name Description Table A-2 Expb signal descriptionExpim Label Table A-3 Expim signal descriptionsLM-EP20K1000E Description Figure A-4 J7 pin locations Logic analyzer connectorCLK1 Table A-4 J7 connector pinout Signal PinMulti-ICE Jtag Figure A-5 Multi-ICE connector pinoutMechanical Specification Mechanical information Figure B-1 Board dimensions top viewFigure B-2 Bottom board dimensions viewed from top side DB9DUAL Connector referenceDB9STRAIGHT FCI Multi-ICE GlossarySynchronous Serial Port ADC Can IndexDAC GpioGpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn Expa A-2Lmleds Lmlock LMOSC1