Arm Enterprises IM-AD1 manual Expb

Page 78

Signal Descriptions

A.2 EXPB

Figure A-2 shows the pin numbers of the socket EXPB on the underside of the interface module.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

H0

H1

H3

H4

H6

H7

H9

H10

H12

H13

H15

H16

H18

H19

H21

H22

H24

H25

H27

H28

H30

H31

J1

J2

J4

J5

J7

5V

5V

5V

GND

GND

F1

H2

GND

GND

F4

H5

GND

GND

F7

H8

GND

GND

F10

H11

GND

GND

F13

H14

GND

GND

F16

H17

GND

GND

F19

H20

GND

GND

F22

H23

GND

GND

F25

H26

GND

GND

F28

H29

GND

GND

F31

J0

GND

GND

J10

J3

GND

GND

J13

J6

J16

GND

-12V

3V3

-12V

3V3

-12V

3V3

F0

F2

F3

F5

F6

F8

F9

F11

F12

F14

F15

F17

F18

F20

F21

F23

F24

F26

F27

F29

F30

J8

J9

J11

J12

J14

J15

12V

12V

12V

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

Figure A-2 EXPB socket pin numbering

A-4

Copyright © 2001-2003. All rights reserved.

ARM DUI 0163B

Image 78

Contents Integrator/IM-AD1 Integrator/IM-AD1 User GuideConformance Notices Copyright 2001-2003. All rights reserved Integrator/IM-AD1 User Guide Chapter IntroductionAppendix a Signal Descriptions Preface Using this book About this bookIntended audience Typographical conventions Further readingARM publications Third-party documents Feedback Feedback on this documentFeedback on the Integrator/IM-AD1 Xii Introduction About the Integrator/IM-AD1 ARM DUI 0163BIntegrator/IM-AD1 layout Interface module features and architecture FeaturesIntegrator/IM-AD1 block diagram ArchitectureConfig LED Links and LEDsCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Fitting the interface module Assembled Integrator development systemSetting up the logic module Switch 2 Closed Switch 3 Open Switch 4 OpenRunning the test software Hardware Reference Hardware Reference Uart interface Serial interface signal assignment Signal nameConnector DescriptionSerial connector pinout Serial connector signal assignment Pin J18 Type DescriptionSPI signals Signal SPIPWM interface signals Signal PWM interfaceShows the signal assignment PWM connector signals Pin J14 J10 DescriptionStepper motor interface Functional descriptionStepper motor interface signal summary Therefore, with a 0.1Ω sense resistor fittedStepper motor connectors Stepper motor interface signalsStepper motor connector signals Pin J19 J23 Description VSSGpio connectors J16 and J17 GpioHardware Reference Can interface U13Buffer Can interface signal assignment Signal IMBBANK28 IMBBANK29IMBBANK30 Can connector signal assignments Pin GNDADC and DAC interfaces 10 ADC and DAC interface architectureIMABANK50 IMABANK48IMABANK49 IMABANK5111shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About the design example About PrimeCellsExample architecture Vhdl file descriptions File DescriptionExample memory map Address assignment of logic modules Integrator system memory mapIntegrator/IM-AD1 memory map Logic module addresses Position Bits StackIntegrator/IM-AD1 memory map Device Address Gpiob StepperbGpioa SsramExample APB register peripheral Logic module registersOffset address Name Type Function Oscillator divisor registers LMOSCx registers Bits Name Access Function RDWVDW User LEDs control register Bits Name Access FunctionOscillator lock register Push button interrupt registerSwitches register Uart SPICS1 SPI chip select registerSPICS2 SPICS0Synchronous serial port PWM controller Cont Offset Name Access Function AddressStepper motor peripheral CountStepper x control register Docount SinglestepDIR Stepx count register Stepx speed registerData output set register Read data output pinsAddress offset Name Access Size Function Read data input registerData direction Gpio direction control 1 bitSsram interface Interrupt Interrupt source Source number Vectored interrupt controllerInterrupt sources CAN1Reference Design Example Can controller interface Can reset control registerCanreset CANxBaseAdcstatus ADC and DAC interface16 ADC and DAC interface registers ADC2BUSYPeripheral information block 18 PIB entry formatBits Name Function Signal Descriptions Expa Table A-1 AHB signal assignment Pin label Signal DescriptionExpb Table A-2 Expb signal description Pin label Name DescriptionExpim Table A-3 Expim signal descriptions LabelLM-EP20K1000E Description Logic analyzer connector Figure A-4 J7 pin locationsTable A-4 J7 connector pinout Signal Pin CLK1Figure A-5 Multi-ICE connector pinout Multi-ICE JtagMechanical Specification Figure B-1 Board dimensions top view Mechanical informationFigure B-2 Bottom board dimensions viewed from top side Connector reference DB9DUALDB9STRAIGHT FCI Glossary Multi-ICESynchronous Serial Port DAC IndexADC Can GpioExpa A-2 Gpiodataclr Gpiodatain Gpiodataout Gpiodataset GpiodirnLmleds Lmlock LMOSC1